mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
24ba4fa9e1
Differential Revision: http://reviews.llvm.org/D4017 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210770 91177308-0d34-0410-b5e6-96231b3b80d8
605 lines
24 KiB
TableGen
605 lines
24 KiB
TableGen
//=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips32r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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include "Mips32r6InstrFormats.td"
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// Notes about removals/changes from MIPS32r6:
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// Unclear: ssnop
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// Reencoded: cache, pref
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// Reencoded: clo, clz
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// Reencoded: jr -> jalr
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// Reencoded: jr.hb -> jalr.hb
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// Reencoded: ldc2
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// Reencoded: ll, sc
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// Reencoded: lwc2
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// Reencoded: sdbbp
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// Reencoded: sdc2
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// Reencoded: swc2
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// Removed: bc1any2, bc1any4
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// Removed: bc2[ft]
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// Removed: bc2f, bc2t
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// Removed: bgezal
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// Removed: bltzal
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// Removed: c.cond.fmt, bc1[ft]
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// Removed: jalx
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// Removed: ldxc1
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// Removed: luxc1
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// Removed: lwxc1
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// Removed: movf, movt
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// Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
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// Removed: movn, movz
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// Removed: prefx
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// Removed: sdxc1
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// Removed: suxc1
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// Removed: swxc1
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// Rencoded: [ls][wd]c2
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def brtarget21 : Operand<OtherVT> {
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let EncoderMethod = "getBranchTarget21OpValue";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTarget21";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def brtarget26 : Operand<OtherVT> {
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let EncoderMethod = "getBranchTarget26OpValue";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTarget26";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def jmpoffset16 : Operand<OtherVT> {
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let EncoderMethod = "getJumpOffset16OpValue";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def calloffset16 : Operand<iPTR> {
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let EncoderMethod = "getJumpOffset16OpValue";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
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class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
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class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
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class AUI_ENC : AUI_FM;
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class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
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class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
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class BC_ENC : BRANCH_OFF26_FM<0b110010>;
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class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
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DecodeDisambiguates<"AddiGroupBranch">;
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class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
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DecodeDisambiguatedBy<"DaddiGroupBranch">;
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class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
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DecodeDisambiguates<"DaddiGroupBranch">;
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class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
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DecodeDisambiguatedBy<"DaddiGroupBranch">;
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class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
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DecodeDisambiguates<"BgtzlGroupBranch">;
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class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
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DecodeDisambiguatedBy<"BlezlGroupBranch">;
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class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
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DecodeDisambiguatedBy<"BlezGroupBranch">;
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class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
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DecodeDisambiguates<"BlezlGroupBranch">;
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class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
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DecodeDisambiguatedBy<"BgtzGroupBranch">;
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class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
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DecodeDisambiguatedBy<"BlezlGroupBranch">;
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class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
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DecodeDisambiguates<"BgtzGroupBranch">;
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class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
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DecodeDisambiguatedBy<"BgtzlGroupBranch">;
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class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
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class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
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DecodeDisambiguates<"BlezGroupBranch">;
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class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
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class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
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class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
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class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
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class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
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class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
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class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
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class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
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class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
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class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
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DecodeDisambiguatedBy<"BlezGroupBranch">;
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class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
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DecodeDisambiguatedBy<"DaddiGroupBranch">;
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class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
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DecodeDisambiguatedBy<"AddiGroupBranch">;
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class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
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class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
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class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
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class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
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class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
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class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
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class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
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class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
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class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
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class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
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class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
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class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
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class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
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class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
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class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
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class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
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class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
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class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
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class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
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class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
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class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
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class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
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class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
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class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
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class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
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class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
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class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
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class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
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class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
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class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
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class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
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class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
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class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
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class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
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class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
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dag OutOperandList = (outs FGROpnd:$fd);
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dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
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string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
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list<dag> Pattern = [];
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Multiclasses
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//
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//===----------------------------------------------------------------------===//
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multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
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RegisterOperand FGROpnd>{
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def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
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CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
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CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
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CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
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CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
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CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
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CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
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CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
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CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
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CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
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CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
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CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
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CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
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CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
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CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
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CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
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CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
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ISA_MIPS32R6;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins ImmOpnd:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
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list<dag> Pattern = [];
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}
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class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
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class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
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class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
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class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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Operand ImmOpnd> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
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list<dag> Pattern = [];
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}
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class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
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class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
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list<dag> Pattern = [];
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}
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class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
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class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
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class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
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list<dag> Pattern = [];
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}
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class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
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class BRANCH_DESC_BASE {
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bit isBranch = 1;
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bit isTerminator = 1;
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bit hasDelaySlot = 0;
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}
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class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$offset");
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bit isBarrier = 1;
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}
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class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
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list<Register> Defs = [AT];
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}
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class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
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list<Register> Defs = [AT];
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}
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class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
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list<Register> Defs = [AT];
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}
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class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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}
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class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
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class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
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class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
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class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
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class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
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class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
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class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
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class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
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class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
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class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
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class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
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class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
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dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
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dag OutOperandList = (outs);
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string AsmString = instr_asm;
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bit hasDelaySlot = 1;
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}
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class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
|
|
class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
|
|
|
|
class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
|
|
dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
|
|
dag OutOperandList = (outs);
|
|
string AsmString = instr_asm;
|
|
bit hasDelaySlot = 1;
|
|
}
|
|
|
|
class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
|
|
class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
|
|
|
|
class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
|
|
class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
|
|
|
|
class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
|
|
RegisterOperand GPROpnd> {
|
|
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
|
|
string AsmString = !strconcat(opstr, "\t$rt, $offset");
|
|
list<dag> Pattern = [];
|
|
bit isTerminator = 1;
|
|
bit hasDelaySlot = 0;
|
|
string DecoderMethod = "DecodeSimm16";
|
|
}
|
|
|
|
class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
|
|
GPR32Opnd> {
|
|
bit isCall = 1;
|
|
list<Register> Defs = [RA];
|
|
}
|
|
|
|
class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
|
|
bit isBarrier = 1;
|
|
list<Register> Defs = [AT];
|
|
}
|
|
|
|
class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
|
|
bit isBranch = 1;
|
|
bit isIndirectBranch = 1;
|
|
bit hasDelaySlot = 1;
|
|
bit isTerminator=1;
|
|
bit isBarrier=1;
|
|
}
|
|
|
|
class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
|
|
dag OutOperandList = (outs GPROpnd:$rd);
|
|
dag InOperandList = (ins GPROpnd:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
|
|
list<dag> Pattern = [];
|
|
}
|
|
|
|
class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
|
|
|
|
class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
|
SDPatternOperator Op=null_frag> {
|
|
dag OutOperandList = (outs GPROpnd:$rd);
|
|
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
|
|
list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
|
|
|
|
// This instruction doesn't trap division by zero itself. We must insert
|
|
// teq instructions as well.
|
|
bit usesCustomInserter = 1;
|
|
}
|
|
|
|
class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
|
|
class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
|
|
class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
|
|
class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
|
|
|
|
class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
|
|
list<Register> Defs = [RA];
|
|
}
|
|
|
|
class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
|
|
list<Register> Defs = [RA];
|
|
}
|
|
|
|
class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
|
|
list<Register> Defs = [RA];
|
|
}
|
|
|
|
class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
|
|
list<Register> Defs = [RA];
|
|
}
|
|
|
|
class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
|
|
list<Register> Defs = [RA];
|
|
}
|
|
|
|
class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
|
|
list<Register> Defs = [RA];
|
|
}
|
|
|
|
class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
|
SDPatternOperator Op=null_frag> {
|
|
dag OutOperandList = (outs GPROpnd:$rd);
|
|
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
|
|
list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
|
|
}
|
|
|
|
class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
|
|
class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
|
|
class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
|
|
class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
|
|
|
|
class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
|
dag OutOperandList = (outs FGROpnd:$fd);
|
|
dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
|
|
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
|
|
list<dag> Pattern = [];
|
|
string Constraints = "$fd_in = $fd";
|
|
}
|
|
|
|
class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
|
|
class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
|
|
|
|
class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
|
|
dag OutOperandList = (outs GPROpnd:$rd);
|
|
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
|
|
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
|
|
list<dag> Pattern = [];
|
|
}
|
|
|
|
class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
|
|
class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
|
|
|
|
class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
|
|
class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
|
|
class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
|
|
class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
|
|
|
|
class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
|
dag OutOperandList = (outs FGROpnd:$fd);
|
|
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
|
|
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
|
|
list<dag> Pattern = [];
|
|
}
|
|
|
|
class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
|
|
class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
|
|
class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
|
|
class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
|
|
|
|
class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
|
|
class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
|
|
class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
|
|
class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
|
|
|
|
class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
|
dag OutOperandList = (outs FGROpnd:$fd);
|
|
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
|
|
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
|
|
list<dag> Pattern = [];
|
|
}
|
|
|
|
class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
|
|
class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
|
|
class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
|
|
class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
|
|
|
|
class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
|
|
dag OutOperandList = (outs FGROpnd:$fd);
|
|
dag InOperandList = (ins FGROpnd:$fs);
|
|
string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
|
|
list<dag> Pattern = [];
|
|
}
|
|
|
|
class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
|
|
class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
|
|
class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
|
|
class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// Instruction Definitions
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
|
|
def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
|
|
def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
|
|
def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
|
|
def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
|
|
def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
|
|
def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
|
|
def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
|
|
def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
|
|
def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
|
|
def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
|
|
def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
|
|
def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
|
|
def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
|
|
def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
|
|
def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
|
|
def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
|
|
def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
|
|
def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
|
|
def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
|
|
def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
|
|
def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
|
|
def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
|
|
def BLTC; // Also aliased to bgtc with operands swapped
|
|
def BLTUC; // Also aliased to bgtuc with operands swapped
|
|
def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
|
|
def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
|
|
def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
|
|
def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
|
|
def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
|
|
def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
|
|
def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
|
|
def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
|
|
def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
|
|
defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
|
|
defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
|
|
def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
|
|
def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
|
|
def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
|
|
def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
|
|
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
|
|
// def LSA; // See MSA
|
|
def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
|
|
def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
|
|
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
|
|
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
|
|
def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
|
|
def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
|
|
def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
|
|
def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
|
|
def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
|
|
def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
|
|
def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
|
|
def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
|
|
def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
|
|
def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
|
|
def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
|
|
def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
|
|
def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
|
|
def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
|
|
def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
|
|
def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
|
|
def NAL; // BAL with rd=0
|
|
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
|
|
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
|
|
def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6;
|
|
def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
|
|
def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
|
|
def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6;
|
|
def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
|
|
def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
|
|
def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
|
|
def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
|