Hao Liu 75ad488c41 [AArch64]Select wide immediate offset into [Base+XReg] addressing mode ... e.g Currently we'll generate following instructions if the immediate is too wide: MOV X0, WideImmediate ADD X1, BaseReg, X0 LDR X2, [X1, 0] Using [Base+XReg] addressing mode can save one ADD as following: MOV X0, WideImmediate LDR X2, [BaseReg, X0] Differential Revision: http://reviews.llvm.org/D5477 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219665 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-14 06:50:36 +00:00
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AArch64	[AArch64]Select wide immediate offset into [Base+XReg] addressing mode	2014-10-14 06:50:36 +00:00
ARM	Adds support for the Cortex-A17 to the ARM backend	2014-10-13 10:22:19 +00:00
CPP
Generic	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Hexagon	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Inputs	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Mips	[mips] Mark redundant instructions with a comment in test/CodeGen/Mips/Fast-ISel/icmpa.ll.	2014-10-13 10:18:02 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX	Revert r216862 due to a performance regression	2014-10-01 15:22:13 +00:00
PowerPC	Improve sqrt estimate algorithm (fast-math)	2014-10-09 21:26:35 +00:00
R600	llvm/test/CodeGen: Some tests don't REQUIRE asserts any more. Remove them.	2014-10-12 06:47:47 +00:00
SPARC	Add back tests for empty function in SPARC and PowerPC.	2014-09-15 22:11:07 +00:00
SystemZ
Thumb	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Thumb2	[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5	2014-10-01 13:13:18 +00:00
X86	Fix a broadcast related regression on the vector shuffle lowering.	2014-10-13 16:16:16 +00:00
XCore	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00