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151a5da534
LocalStackSlotPass assumes that isFrameOffsetLegal doesn't change its answer when the base register changes. Unfortunately this isn't true in thumb1, where SP-based loads allow a larger offset than non-SP-based loads, and this causes the base register reuse code to generate instructions that are unencodable, causing an assertion failure. Solve this by adding a BaseReg parameter to isFrameOffsetLegal, which ARMBaseRegisterInfo can then make use of to give the correct answer. Differential Revision: http://reviews.llvm.org/D8419 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232825 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
4.3 KiB
C++
113 lines
4.3 KiB
C++
//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
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#define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
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#include "PPC.h"
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#include "llvm/ADT/DenseMap.h"
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#define GET_REGINFO_HEADER
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#include "PPCGenRegisterInfo.inc"
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namespace llvm {
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class PPCRegisterInfo : public PPCGenRegisterInfo {
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DenseMap<unsigned, unsigned> ImmToIdxMap;
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const PPCTargetMachine &TM;
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public:
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PPCRegisterInfo(const PPCTargetMachine &TM);
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &MF) const override;
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/// Code Generation virtual methods...
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const override;
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const uint32_t *getNoPreservedMask() const;
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void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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/// We require the register scavenger.
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bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
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return true;
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}
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bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
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return true;
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}
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void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
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void lowerCRSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRRestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRBitSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRBitRestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerVRSAVERestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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int &FrameIdx) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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// Support for virtual base registers.
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg, int FrameIdx,
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int64_t Offset) const override;
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void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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int64_t Offset) const override;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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// Base pointer (stack realignment) support.
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unsigned getBaseRegister(const MachineFunction &MF) const;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const;
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bool needsStackRealignment(const MachineFunction &MF) const override;
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};
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} // end namespace llvm
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#endif
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