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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
1212 lines
43 KiB
C++
1212 lines
43 KiB
C++
//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs loop invariant code motion on machine instructions. We
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// attempt to remove as much code from the body of a loop as possible.
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//
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// This pass does not attempt to throttle itself to limit register pressure.
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// The register allocation phases are expected to perform rematerialization
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// to recover when register pressure is high.
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//
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// This pass is not intended to be a replacement or a complete alternative
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// for the LLVM-IR-level LICM pass. It is only designed to hoist simple
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// constructs that are not exposed before lowering and instruction selection.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-licm"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(NumHoisted,
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"Number of machine instructions hoisted out of loops");
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STATISTIC(NumLowRP,
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"Number of instructions hoisted in low reg pressure situation");
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STATISTIC(NumHighLatency,
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"Number of high latency instructions hoisted");
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STATISTIC(NumCSEed,
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"Number of hoisted machine instructions CSEed");
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STATISTIC(NumPostRAHoisted,
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"Number of machine instructions hoisted out of loops post regalloc");
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namespace {
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class MachineLICM : public MachineFunctionPass {
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bool PreRegAlloc;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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const TargetLowering *TLI;
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const TargetRegisterInfo *TRI;
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const MachineFrameInfo *MFI;
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MachineRegisterInfo *MRI;
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const InstrItineraryData *InstrItins;
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// Various analyses that we use...
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AliasAnalysis *AA; // Alias analysis info.
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MachineLoopInfo *MLI; // Current MachineLoopInfo
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MachineDominatorTree *DT; // Machine dominator tree for the cur loop
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// State that is updated as we process loops
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bool Changed; // True if a loop is changed.
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bool FirstInLoop; // True if it's the first LICM in the loop.
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MachineLoop *CurLoop; // The current loop we are working on.
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MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
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BitVector AllocatableSet;
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// Track 'estimated' register pressure.
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SmallSet<unsigned, 32> RegSeen;
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SmallVector<unsigned, 8> RegPressure;
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// Register pressure "limit" per register class. If the pressure
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// is higher than the limit, then it's considered high.
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SmallVector<unsigned, 8> RegLimit;
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// Register pressure on path leading from loop preheader to current BB.
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SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
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// For each opcode, keep a list of potential CSE instructions.
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DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
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public:
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static char ID; // Pass identification, replacement for typeid
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MachineLICM() :
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MachineFunctionPass(ID), PreRegAlloc(true) {
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initializeMachineLICMPass(*PassRegistry::getPassRegistry());
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}
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explicit MachineLICM(bool PreRA) :
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MachineFunctionPass(ID), PreRegAlloc(PreRA) {
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initializeMachineLICMPass(*PassRegistry::getPassRegistry());
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const { return "Machine Instruction LICM"; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreserved<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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RegSeen.clear();
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RegPressure.clear();
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RegLimit.clear();
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BackTrace.clear();
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for (DenseMap<unsigned,std::vector<const MachineInstr*> >::iterator
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CI = CSEMap.begin(), CE = CSEMap.end(); CI != CE; ++CI)
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CI->second.clear();
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CSEMap.clear();
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}
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private:
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/// CandidateInfo - Keep track of information about hoisting candidates.
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struct CandidateInfo {
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MachineInstr *MI;
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unsigned Def;
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int FI;
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CandidateInfo(MachineInstr *mi, unsigned def, int fi)
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: MI(mi), Def(def), FI(fi) {}
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};
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/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
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/// invariants out to the preheader.
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void HoistRegionPostRA();
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/// HoistPostRA - When an instruction is found to only use loop invariant
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/// operands that is safe to hoist, this instruction is called to do the
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/// dirty work.
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void HoistPostRA(MachineInstr *MI, unsigned Def);
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/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
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/// gather register def and frame object update information.
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void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
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SmallSet<int, 32> &StoredFIs,
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SmallVector<CandidateInfo, 32> &Candidates);
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/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
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/// current loop.
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void AddToLiveIns(unsigned Reg);
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/// IsLICMCandidate - Returns true if the instruction may be a suitable
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/// candidate for LICM. e.g. If the instruction is a call, then it's
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/// obviously not safe to hoist it.
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bool IsLICMCandidate(MachineInstr &I);
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/// IsLoopInvariantInst - Returns true if the instruction is loop
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/// invariant. I.e., all virtual register operands are defined outside of
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/// the loop, physical registers aren't accessed (explicitly or implicitly),
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/// and the instruction is hoistable.
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///
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bool IsLoopInvariantInst(MachineInstr &I);
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/// HasAnyPHIUse - Return true if the specified register is used by any
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/// phi node.
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bool HasAnyPHIUse(unsigned Reg) const;
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/// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
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/// and an use in the current loop, return true if the target considered
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/// it 'high'.
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bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
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unsigned Reg) const;
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bool IsCheapInstruction(MachineInstr &MI) const;
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/// CanCauseHighRegPressure - Visit BBs from header to current BB,
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/// check if hoisting an instruction of the given cost matrix can cause high
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/// register pressure.
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bool CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost);
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/// UpdateBackTraceRegPressure - Traverse the back trace from header to
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/// the current block and update their register pressures to reflect the
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/// effect of hoisting MI from the current block to the preheader.
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void UpdateBackTraceRegPressure(const MachineInstr *MI);
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/// IsProfitableToHoist - Return true if it is potentially profitable to
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/// hoist the given loop invariant.
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bool IsProfitableToHoist(MachineInstr &MI);
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/// HoistRegion - Walk the specified region of the CFG (defined by all
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/// blocks dominated by the specified block, and that are in the current
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/// loop) in depth first order w.r.t the DominatorTree. This allows us to
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/// visit definitions before uses, allowing us to hoist a loop body in one
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/// pass without iteration.
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///
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void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false);
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/// InitRegPressure - Find all virtual register references that are liveout
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/// of the preheader to initialize the starting "register pressure". Note
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/// this does not count live through (livein but not used) registers.
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void InitRegPressure(MachineBasicBlock *BB);
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/// UpdateRegPressure - Update estimate of register pressure after the
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/// specified instruction.
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void UpdateRegPressure(const MachineInstr *MI);
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/// ExtractHoistableLoad - Unfold a load from the given machineinstr if
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/// the load itself could be hoisted. Return the unfolded and hoistable
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/// load, or null if the load couldn't be unfolded or if it wouldn't
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/// be hoistable.
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MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
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/// LookForDuplicate - Find an instruction amount PrevMIs that is a
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/// duplicate of MI. Return this instruction if it's found.
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const MachineInstr *LookForDuplicate(const MachineInstr *MI,
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std::vector<const MachineInstr*> &PrevMIs);
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/// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
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/// the preheader that compute the same value. If it's found, do a RAU on
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/// with the definition of the existing instruction rather than hoisting
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/// the instruction to the preheader.
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bool EliminateCSE(MachineInstr *MI,
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DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
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/// Hoist - When an instruction is found to only use loop invariant operands
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/// that is safe to hoist, this instruction is called to do the dirty work.
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/// It returns true if the instruction is hoisted.
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bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
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/// InitCSEMap - Initialize the CSE map with instructions that are in the
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/// current loop preheader that may become duplicates of instructions that
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/// are hoisted out of the loop.
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void InitCSEMap(MachineBasicBlock *BB);
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/// getCurPreheader - Get the preheader for the current loop, splitting
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/// a critical edge if needed.
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MachineBasicBlock *getCurPreheader();
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};
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} // end anonymous namespace
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char MachineLICM::ID = 0;
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INITIALIZE_PASS_BEGIN(MachineLICM, "machinelicm",
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"Machine Loop Invariant Code Motion", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_END(MachineLICM, "machinelicm",
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"Machine Loop Invariant Code Motion", false, false)
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FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
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return new MachineLICM(PreRegAlloc);
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}
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/// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
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/// loop that has a unique predecessor.
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static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
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// Check whether this loop even has a unique predecessor.
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if (!CurLoop->getLoopPredecessor())
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return false;
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// Ok, now check to see if any of its outer loops do.
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for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
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if (L->getLoopPredecessor())
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return false;
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// None of them did, so this is the outermost with a unique predecessor.
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return true;
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}
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bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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if (PreRegAlloc)
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DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
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else
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DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
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DEBUG(dbgs() << MF.getFunction()->getName() << " ********\n");
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Changed = FirstInLoop = false;
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TM = &MF.getTarget();
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TII = TM->getInstrInfo();
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TLI = TM->getTargetLowering();
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TRI = TM->getRegisterInfo();
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MFI = MF.getFrameInfo();
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MRI = &MF.getRegInfo();
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InstrItins = TM->getInstrItineraryData();
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AllocatableSet = TRI->getAllocatableSet(MF);
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if (PreRegAlloc) {
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// Estimate register pressure during pre-regalloc pass.
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unsigned NumRC = TRI->getNumRegClasses();
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RegPressure.resize(NumRC);
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std::fill(RegPressure.begin(), RegPressure.end(), 0);
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RegLimit.resize(NumRC);
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I)
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RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
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}
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// Get our Loop information...
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MLI = &getAnalysis<MachineLoopInfo>();
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DT = &getAnalysis<MachineDominatorTree>();
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AA = &getAnalysis<AliasAnalysis>();
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SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
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while (!Worklist.empty()) {
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CurLoop = Worklist.pop_back_val();
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CurPreheader = 0;
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// If this is done before regalloc, only visit outer-most preheader-sporting
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// loops.
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if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
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Worklist.append(CurLoop->begin(), CurLoop->end());
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continue;
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}
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if (!PreRegAlloc)
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HoistRegionPostRA();
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else {
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// CSEMap is initialized for loop header when the first instruction is
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// being hoisted.
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MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
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FirstInLoop = true;
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HoistRegion(N, true);
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CSEMap.clear();
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}
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}
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return Changed;
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}
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/// InstructionStoresToFI - Return true if instruction stores to the
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/// specified frame.
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static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
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for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
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oe = MI->memoperands_end(); o != oe; ++o) {
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if (!(*o)->isStore() || !(*o)->getValue())
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continue;
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if (const FixedStackPseudoSourceValue *Value =
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dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
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if (Value->getFrameIndex() == FI)
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return true;
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}
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}
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return false;
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}
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/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
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/// gather register def and frame object update information.
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void MachineLICM::ProcessMI(MachineInstr *MI,
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unsigned *PhysRegDefs,
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SmallSet<int, 32> &StoredFIs,
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SmallVector<CandidateInfo, 32> &Candidates) {
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bool RuledOut = false;
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bool HasNonInvariantUse = false;
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unsigned Def = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isFI()) {
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// Remember if the instruction stores to the frame index.
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int FI = MO.getIndex();
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if (!StoredFIs.count(FI) &&
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MFI->isSpillSlotObjectIndex(FI) &&
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InstructionStoresToFI(MI, FI))
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StoredFIs.insert(FI);
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HasNonInvariantUse = true;
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continue;
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}
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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"Not expecting virtual register!");
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if (!MO.isDef()) {
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if (Reg && PhysRegDefs[Reg])
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// If it's using a non-loop-invariant register, then it's obviously not
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// safe to hoist.
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HasNonInvariantUse = true;
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continue;
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}
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if (MO.isImplicit()) {
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++PhysRegDefs[Reg];
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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++PhysRegDefs[*AS];
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if (!MO.isDead())
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// Non-dead implicit def? This cannot be hoisted.
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RuledOut = true;
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// No need to check if a dead implicit def is also defined by
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// another instruction.
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continue;
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}
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// FIXME: For now, avoid instructions with multiple defs, unless
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// it's a dead implicit def.
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if (Def)
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RuledOut = true;
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else
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Def = Reg;
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// If we have already seen another instruction that defines the same
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// register, then this is not safe.
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if (++PhysRegDefs[Reg] > 1)
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// MI defined register is seen defined by another instruction in
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// the loop, it cannot be a LICM candidate.
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RuledOut = true;
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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if (++PhysRegDefs[*AS] > 1)
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RuledOut = true;
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}
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// Only consider reloads for now and remats which do not have register
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// operands. FIXME: Consider unfold load folding instructions.
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if (Def && !RuledOut) {
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int FI = INT_MIN;
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if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
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(TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
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Candidates.push_back(CandidateInfo(MI, Def, FI));
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}
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}
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/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
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/// invariants out to the preheader.
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void MachineLICM::HoistRegionPostRA() {
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unsigned NumRegs = TRI->getNumRegs();
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unsigned *PhysRegDefs = new unsigned[NumRegs];
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std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
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SmallVector<CandidateInfo, 32> Candidates;
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SmallSet<int, 32> StoredFIs;
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// Walk the entire region, count number of defs for each register, and
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// collect potential LICM candidates.
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const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
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for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
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MachineBasicBlock *BB = Blocks[i];
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// Conservatively treat live-in's as an external def.
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// FIXME: That means a reload that're reused in successor block(s) will not
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// be LICM'ed.
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for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
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E = BB->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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++PhysRegDefs[Reg];
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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++PhysRegDefs[*AS];
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}
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for (MachineBasicBlock::iterator
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MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
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MachineInstr *MI = &*MII;
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ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
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}
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}
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// Now evaluate whether the potential candidates qualify.
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// 1. Check if the candidate defined register is defined by another
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// instruction in the loop.
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// 2. If the candidate is a load from stack slot (always true for now),
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// check if the slot is stored anywhere in the loop.
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for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
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if (Candidates[i].FI != INT_MIN &&
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StoredFIs.count(Candidates[i].FI))
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continue;
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|
|
if (PhysRegDefs[Candidates[i].Def] == 1) {
|
|
bool Safe = true;
|
|
MachineInstr *MI = Candidates[i].MI;
|
|
for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
|
|
const MachineOperand &MO = MI->getOperand(j);
|
|
if (!MO.isReg() || MO.isDef() || !MO.getReg())
|
|
continue;
|
|
if (PhysRegDefs[MO.getReg()]) {
|
|
// If it's using a non-loop-invariant register, then it's obviously
|
|
// not safe to hoist.
|
|
Safe = false;
|
|
break;
|
|
}
|
|
}
|
|
if (Safe)
|
|
HoistPostRA(MI, Candidates[i].Def);
|
|
}
|
|
}
|
|
|
|
delete[] PhysRegDefs;
|
|
}
|
|
|
|
/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
|
|
/// loop, and make sure it is not killed by any instructions in the loop.
|
|
void MachineLICM::AddToLiveIns(unsigned Reg) {
|
|
const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
|
|
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
|
|
MachineBasicBlock *BB = Blocks[i];
|
|
if (!BB->isLiveIn(Reg))
|
|
BB->addLiveIn(Reg);
|
|
for (MachineBasicBlock::iterator
|
|
MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
|
|
MachineInstr *MI = &*MII;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
|
|
if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
|
|
MO.setIsKill(false);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// HoistPostRA - When an instruction is found to only use loop invariant
|
|
/// operands that is safe to hoist, this instruction is called to do the
|
|
/// dirty work.
|
|
void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
|
|
MachineBasicBlock *Preheader = getCurPreheader();
|
|
if (!Preheader) return;
|
|
|
|
// Now move the instructions to the predecessor, inserting it before any
|
|
// terminator instructions.
|
|
DEBUG({
|
|
dbgs() << "Hoisting " << *MI;
|
|
if (Preheader->getBasicBlock())
|
|
dbgs() << " to MachineBasicBlock "
|
|
<< Preheader->getName();
|
|
if (MI->getParent()->getBasicBlock())
|
|
dbgs() << " from MachineBasicBlock "
|
|
<< MI->getParent()->getName();
|
|
dbgs() << "\n";
|
|
});
|
|
|
|
// Splice the instruction to the preheader.
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
|
|
|
|
// Add register to livein list to all the BBs in the current loop since a
|
|
// loop invariant must be kept live throughout the whole loop. This is
|
|
// important to ensure later passes do not scavenge the def register.
|
|
AddToLiveIns(Def);
|
|
|
|
++NumPostRAHoisted;
|
|
Changed = true;
|
|
}
|
|
|
|
/// HoistRegion - Walk the specified region of the CFG (defined by all blocks
|
|
/// dominated by the specified block, and that are in the current loop) in depth
|
|
/// first order w.r.t the DominatorTree. This allows us to visit definitions
|
|
/// before uses, allowing us to hoist a loop body in one pass without iteration.
|
|
///
|
|
void MachineLICM::HoistRegion(MachineDomTreeNode *N, bool IsHeader) {
|
|
assert(N != 0 && "Null dominator tree node?");
|
|
MachineBasicBlock *BB = N->getBlock();
|
|
|
|
// If this subregion is not in the top level loop at all, exit.
|
|
if (!CurLoop->contains(BB)) return;
|
|
|
|
MachineBasicBlock *Preheader = getCurPreheader();
|
|
if (!Preheader)
|
|
return;
|
|
|
|
if (IsHeader) {
|
|
// Compute registers which are livein into the loop headers.
|
|
RegSeen.clear();
|
|
BackTrace.clear();
|
|
InitRegPressure(Preheader);
|
|
}
|
|
|
|
// Remember livein register pressure.
|
|
BackTrace.push_back(RegPressure);
|
|
|
|
for (MachineBasicBlock::iterator
|
|
MII = BB->begin(), E = BB->end(); MII != E; ) {
|
|
MachineBasicBlock::iterator NextMII = MII; ++NextMII;
|
|
MachineInstr *MI = &*MII;
|
|
if (!Hoist(MI, Preheader))
|
|
UpdateRegPressure(MI);
|
|
MII = NextMII;
|
|
}
|
|
|
|
// Don't hoist things out of a large switch statement. This often causes
|
|
// code to be hoisted that wasn't going to be executed, and increases
|
|
// register pressure in a situation where it's likely to matter.
|
|
if (BB->succ_size() < 25) {
|
|
const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
|
|
for (unsigned I = 0, E = Children.size(); I != E; ++I)
|
|
HoistRegion(Children[I]);
|
|
}
|
|
|
|
BackTrace.pop_back();
|
|
}
|
|
|
|
static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
|
|
return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
|
|
}
|
|
|
|
/// InitRegPressure - Find all virtual register references that are liveout of
|
|
/// the preheader to initialize the starting "register pressure". Note this
|
|
/// does not count live through (livein but not used) registers.
|
|
void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
|
|
std::fill(RegPressure.begin(), RegPressure.end(), 0);
|
|
|
|
// If the preheader has only a single predecessor and it ends with a
|
|
// fallthrough or an unconditional branch, then scan its predecessor for live
|
|
// defs as well. This happens whenever the preheader is created by splitting
|
|
// the critical edge from the loop predecessor to the loop header.
|
|
if (BB->pred_size() == 1) {
|
|
MachineBasicBlock *TBB = 0, *FBB = 0;
|
|
SmallVector<MachineOperand, 4> Cond;
|
|
if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
|
|
InitRegPressure(*BB->pred_begin());
|
|
}
|
|
|
|
for (MachineBasicBlock::iterator MII = BB->begin(), E = BB->end();
|
|
MII != E; ++MII) {
|
|
MachineInstr *MI = &*MII;
|
|
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || MO.isImplicit())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
continue;
|
|
|
|
bool isNew = RegSeen.insert(Reg);
|
|
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
|
|
EVT VT = *RC->vt_begin();
|
|
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
|
|
if (MO.isDef())
|
|
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
|
|
else {
|
|
bool isKill = isOperandKill(MO, MRI);
|
|
if (isNew && !isKill)
|
|
// Haven't seen this, it must be a livein.
|
|
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
|
|
else if (!isNew && isKill)
|
|
RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// UpdateRegPressure - Update estimate of register pressure after the
|
|
/// specified instruction.
|
|
void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
|
|
if (MI->isImplicitDef())
|
|
return;
|
|
|
|
SmallVector<unsigned, 4> Defs;
|
|
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || MO.isImplicit())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
continue;
|
|
|
|
bool isNew = RegSeen.insert(Reg);
|
|
if (MO.isDef())
|
|
Defs.push_back(Reg);
|
|
else if (!isNew && isOperandKill(MO, MRI)) {
|
|
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
|
|
EVT VT = *RC->vt_begin();
|
|
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
|
|
unsigned RCCost = TLI->getRepRegClassCostFor(VT);
|
|
|
|
if (RCCost > RegPressure[RCId])
|
|
RegPressure[RCId] = 0;
|
|
else
|
|
RegPressure[RCId] -= RCCost;
|
|
}
|
|
}
|
|
|
|
while (!Defs.empty()) {
|
|
unsigned Reg = Defs.pop_back_val();
|
|
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
|
|
EVT VT = *RC->vt_begin();
|
|
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
|
|
unsigned RCCost = TLI->getRepRegClassCostFor(VT);
|
|
RegPressure[RCId] += RCCost;
|
|
}
|
|
}
|
|
|
|
/// IsLICMCandidate - Returns true if the instruction may be a suitable
|
|
/// candidate for LICM. e.g. If the instruction is a call, then it's obviously
|
|
/// not safe to hoist it.
|
|
bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
|
|
// Check if it's safe to move the instruction.
|
|
bool DontMoveAcrossStore = true;
|
|
if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
/// IsLoopInvariantInst - Returns true if the instruction is loop
|
|
/// invariant. I.e., all virtual register operands are defined outside of the
|
|
/// loop, physical registers aren't accessed explicitly, and there are no side
|
|
/// effects that aren't captured by the operands or other flags.
|
|
///
|
|
bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
|
|
if (!IsLICMCandidate(I))
|
|
return false;
|
|
|
|
// The instruction is loop invariant if all of its operands are.
|
|
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = I.getOperand(i);
|
|
|
|
if (!MO.isReg())
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
|
|
// Don't hoist an instruction that uses or defines a physical register.
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
if (MO.isUse()) {
|
|
// If the physreg has no defs anywhere, it's just an ambient register
|
|
// and we can freely move its uses. Alternatively, if it's allocatable,
|
|
// it could get allocated to something with a def during allocation.
|
|
if (!MRI->def_empty(Reg))
|
|
return false;
|
|
if (AllocatableSet.test(Reg))
|
|
return false;
|
|
// Check for a def among the register's aliases too.
|
|
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
|
|
unsigned AliasReg = *Alias;
|
|
if (!MRI->def_empty(AliasReg))
|
|
return false;
|
|
if (AllocatableSet.test(AliasReg))
|
|
return false;
|
|
}
|
|
// Otherwise it's safe to move.
|
|
continue;
|
|
} else if (!MO.isDead()) {
|
|
// A def that isn't dead. We can't move it.
|
|
return false;
|
|
} else if (CurLoop->getHeader()->isLiveIn(Reg)) {
|
|
// If the reg is live into the loop, we can't hoist an instruction
|
|
// which would clobber it.
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (!MO.isUse())
|
|
continue;
|
|
|
|
assert(MRI->getVRegDef(Reg) &&
|
|
"Machine instr not mapped for this vreg?!");
|
|
|
|
// If the loop contains the definition of an operand, then the instruction
|
|
// isn't loop invariant.
|
|
if (CurLoop->contains(MRI->getVRegDef(Reg)))
|
|
return false;
|
|
}
|
|
|
|
// If we got this far, the instruction is loop invariant!
|
|
return true;
|
|
}
|
|
|
|
|
|
/// HasAnyPHIUse - Return true if the specified register is used by any
|
|
/// phi node.
|
|
bool MachineLICM::HasAnyPHIUse(unsigned Reg) const {
|
|
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
|
|
UE = MRI->use_end(); UI != UE; ++UI) {
|
|
MachineInstr *UseMI = &*UI;
|
|
if (UseMI->isPHI())
|
|
return true;
|
|
// Look pass copies as well.
|
|
if (UseMI->isCopy()) {
|
|
unsigned Def = UseMI->getOperand(0).getReg();
|
|
if (TargetRegisterInfo::isVirtualRegister(Def) &&
|
|
HasAnyPHIUse(Def))
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
|
|
/// and an use in the current loop, return true if the target considered
|
|
/// it 'high'.
|
|
bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
|
|
unsigned DefIdx, unsigned Reg) const {
|
|
if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
|
|
return false;
|
|
|
|
for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
|
|
E = MRI->use_nodbg_end(); I != E; ++I) {
|
|
MachineInstr *UseMI = &*I;
|
|
if (UseMI->isCopyLike())
|
|
continue;
|
|
if (!CurLoop->contains(UseMI->getParent()))
|
|
continue;
|
|
for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = UseMI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse())
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (MOReg != Reg)
|
|
continue;
|
|
|
|
if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
|
|
return true;
|
|
}
|
|
|
|
// Only look at the first in loop use.
|
|
break;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// IsCheapInstruction - Return true if the instruction is marked "cheap" or
|
|
/// the operand latency between its def and a use is one or less.
|
|
bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
|
|
if (MI.getDesc().isAsCheapAsAMove() || MI.isCopyLike())
|
|
return true;
|
|
if (!InstrItins || InstrItins->isEmpty())
|
|
return false;
|
|
|
|
bool isCheap = false;
|
|
unsigned NumDefs = MI.getDesc().getNumDefs();
|
|
for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
|
|
MachineOperand &DefMO = MI.getOperand(i);
|
|
if (!DefMO.isReg() || !DefMO.isDef())
|
|
continue;
|
|
--NumDefs;
|
|
unsigned Reg = DefMO.getReg();
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
continue;
|
|
|
|
if (!TII->hasLowDefLatency(InstrItins, &MI, i))
|
|
return false;
|
|
isCheap = true;
|
|
}
|
|
|
|
return isCheap;
|
|
}
|
|
|
|
/// CanCauseHighRegPressure - Visit BBs from header to current BB, check
|
|
/// if hoisting an instruction of the given cost matrix can cause high
|
|
/// register pressure.
|
|
bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost) {
|
|
for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
|
|
CI != CE; ++CI) {
|
|
if (CI->second <= 0)
|
|
continue;
|
|
|
|
unsigned RCId = CI->first;
|
|
for (unsigned i = BackTrace.size(); i != 0; --i) {
|
|
SmallVector<unsigned, 8> &RP = BackTrace[i-1];
|
|
if (RP[RCId] + CI->second >= RegLimit[RCId])
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// UpdateBackTraceRegPressure - Traverse the back trace from header to the
|
|
/// current block and update their register pressures to reflect the effect
|
|
/// of hoisting MI from the current block to the preheader.
|
|
void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
|
|
if (MI->isImplicitDef())
|
|
return;
|
|
|
|
// First compute the 'cost' of the instruction, i.e. its contribution
|
|
// to register pressure.
|
|
DenseMap<unsigned, int> Cost;
|
|
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || MO.isImplicit())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
continue;
|
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
|
|
EVT VT = *RC->vt_begin();
|
|
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
|
|
unsigned RCCost = TLI->getRepRegClassCostFor(VT);
|
|
if (MO.isDef()) {
|
|
DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
|
|
if (CI != Cost.end())
|
|
CI->second += RCCost;
|
|
else
|
|
Cost.insert(std::make_pair(RCId, RCCost));
|
|
} else if (isOperandKill(MO, MRI)) {
|
|
DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
|
|
if (CI != Cost.end())
|
|
CI->second -= RCCost;
|
|
else
|
|
Cost.insert(std::make_pair(RCId, -RCCost));
|
|
}
|
|
}
|
|
|
|
// Update register pressure of blocks from loop header to current block.
|
|
for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
|
|
SmallVector<unsigned, 8> &RP = BackTrace[i];
|
|
for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
|
|
CI != CE; ++CI) {
|
|
unsigned RCId = CI->first;
|
|
RP[RCId] += CI->second;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// IsProfitableToHoist - Return true if it is potentially profitable to hoist
|
|
/// the given loop invariant.
|
|
bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
|
|
if (MI.isImplicitDef())
|
|
return true;
|
|
|
|
// If the instruction is cheap, only hoist if it is re-materilizable. LICM
|
|
// will increase register pressure. It's probably not worth it if the
|
|
// instruction is cheap.
|
|
// Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
|
|
// these tend to help performance in low register pressure situation. The
|
|
// trade off is it may cause spill in high pressure situation. It will end up
|
|
// adding a store in the loop preheader. But the reload is no more expensive.
|
|
// The side benefit is these loads are frequently CSE'ed.
|
|
if (IsCheapInstruction(MI)) {
|
|
if (!TII->isTriviallyReMaterializable(&MI, AA))
|
|
return false;
|
|
} else {
|
|
// Estimate register pressure to determine whether to LICM the instruction.
|
|
// In low register pressure situation, we can be more aggressive about
|
|
// hoisting. Also, favors hoisting long latency instructions even in
|
|
// moderately high pressure situation.
|
|
// FIXME: If there are long latency loop-invariant instructions inside the
|
|
// loop at this point, why didn't the optimizer's LICM hoist them?
|
|
DenseMap<unsigned, int> Cost;
|
|
for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
if (!MO.isReg() || MO.isImplicit())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
|
continue;
|
|
if (MO.isDef()) {
|
|
if (HasHighOperandLatency(MI, i, Reg)) {
|
|
++NumHighLatency;
|
|
return true;
|
|
}
|
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
|
|
EVT VT = *RC->vt_begin();
|
|
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
|
|
unsigned RCCost = TLI->getRepRegClassCostFor(VT);
|
|
DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
|
|
if (CI != Cost.end())
|
|
CI->second += RCCost;
|
|
else
|
|
Cost.insert(std::make_pair(RCId, RCCost));
|
|
} else if (isOperandKill(MO, MRI)) {
|
|
// Is a virtual register use is a kill, hoisting it out of the loop
|
|
// may actually reduce register pressure or be register pressure
|
|
// neutral.
|
|
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
|
|
EVT VT = *RC->vt_begin();
|
|
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
|
|
unsigned RCCost = TLI->getRepRegClassCostFor(VT);
|
|
DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
|
|
if (CI != Cost.end())
|
|
CI->second -= RCCost;
|
|
else
|
|
Cost.insert(std::make_pair(RCId, -RCCost));
|
|
}
|
|
}
|
|
|
|
// Visit BBs from header to current BB, if hoisting this doesn't cause
|
|
// high register pressure, then it's safe to proceed.
|
|
if (!CanCauseHighRegPressure(Cost)) {
|
|
++NumLowRP;
|
|
return true;
|
|
}
|
|
|
|
// High register pressure situation, only hoist if the instruction is going to
|
|
// be remat'ed.
|
|
if (!TII->isTriviallyReMaterializable(&MI, AA) &&
|
|
!MI.isInvariantLoad(AA))
|
|
return false;
|
|
}
|
|
|
|
// If result(s) of this instruction is used by PHIs outside of the loop, then
|
|
// don't hoist it if the instruction because it will introduce an extra copy.
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
if (!MO.isReg() || !MO.isDef())
|
|
continue;
|
|
if (HasAnyPHIUse(MO.getReg()))
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
|
|
// Don't unfold simple loads.
|
|
if (MI->getDesc().canFoldAsLoad())
|
|
return 0;
|
|
|
|
// If not, we may be able to unfold a load and hoist that.
|
|
// First test whether the instruction is loading from an amenable
|
|
// memory location.
|
|
if (!MI->isInvariantLoad(AA))
|
|
return 0;
|
|
|
|
// Next determine the register class for a temporary register.
|
|
unsigned LoadRegIndex;
|
|
unsigned NewOpc =
|
|
TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
|
|
/*UnfoldLoad=*/true,
|
|
/*UnfoldStore=*/false,
|
|
&LoadRegIndex);
|
|
if (NewOpc == 0) return 0;
|
|
const MCInstrDesc &MID = TII->get(NewOpc);
|
|
if (MID.getNumDefs() != 1) return 0;
|
|
const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI);
|
|
// Ok, we're unfolding. Create a temporary register and do the unfold.
|
|
unsigned Reg = MRI->createVirtualRegister(RC);
|
|
|
|
MachineFunction &MF = *MI->getParent()->getParent();
|
|
SmallVector<MachineInstr *, 2> NewMIs;
|
|
bool Success =
|
|
TII->unfoldMemoryOperand(MF, MI, Reg,
|
|
/*UnfoldLoad=*/true, /*UnfoldStore=*/false,
|
|
NewMIs);
|
|
(void)Success;
|
|
assert(Success &&
|
|
"unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
|
|
"succeeded!");
|
|
assert(NewMIs.size() == 2 &&
|
|
"Unfolded a load into multiple instructions!");
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
MBB->insert(MI, NewMIs[0]);
|
|
MBB->insert(MI, NewMIs[1]);
|
|
// If unfolding produced a load that wasn't loop-invariant or profitable to
|
|
// hoist, discard the new instructions and bail.
|
|
if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
|
|
NewMIs[0]->eraseFromParent();
|
|
NewMIs[1]->eraseFromParent();
|
|
return 0;
|
|
}
|
|
|
|
// Update register pressure for the unfolded instruction.
|
|
UpdateRegPressure(NewMIs[1]);
|
|
|
|
// Otherwise we successfully unfolded a load that we can hoist.
|
|
MI->eraseFromParent();
|
|
return NewMIs[0];
|
|
}
|
|
|
|
void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
|
|
for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
|
|
const MachineInstr *MI = &*I;
|
|
unsigned Opcode = MI->getOpcode();
|
|
DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
|
|
CI = CSEMap.find(Opcode);
|
|
if (CI != CSEMap.end())
|
|
CI->second.push_back(MI);
|
|
else {
|
|
std::vector<const MachineInstr*> CSEMIs;
|
|
CSEMIs.push_back(MI);
|
|
CSEMap.insert(std::make_pair(Opcode, CSEMIs));
|
|
}
|
|
}
|
|
}
|
|
|
|
const MachineInstr*
|
|
MachineLICM::LookForDuplicate(const MachineInstr *MI,
|
|
std::vector<const MachineInstr*> &PrevMIs) {
|
|
for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
|
|
const MachineInstr *PrevMI = PrevMIs[i];
|
|
if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : 0)))
|
|
return PrevMI;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
bool MachineLICM::EliminateCSE(MachineInstr *MI,
|
|
DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
|
|
// Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
|
|
// the undef property onto uses.
|
|
if (CI == CSEMap.end() || MI->isImplicitDef())
|
|
return false;
|
|
|
|
if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
|
|
DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
|
|
|
|
// Replace virtual registers defined by MI by their counterparts defined
|
|
// by Dup.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
|
|
// Physical registers may not differ here.
|
|
assert((!MO.isReg() || MO.getReg() == 0 ||
|
|
!TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
|
|
MO.getReg() == Dup->getOperand(i).getReg()) &&
|
|
"Instructions with different phys regs are not identical!");
|
|
|
|
if (MO.isReg() && MO.isDef() &&
|
|
!TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
|
|
MRI->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
|
|
MRI->clearKillFlags(Dup->getOperand(i).getReg());
|
|
}
|
|
}
|
|
MI->eraseFromParent();
|
|
++NumCSEed;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// Hoist - When an instruction is found to use only loop invariant operands
|
|
/// that are safe to hoist, this instruction is called to do the dirty work.
|
|
///
|
|
bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
|
|
// First check whether we should hoist this instruction.
|
|
if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
|
|
// If not, try unfolding a hoistable load.
|
|
MI = ExtractHoistableLoad(MI);
|
|
if (!MI) return false;
|
|
}
|
|
|
|
// Now move the instructions to the predecessor, inserting it before any
|
|
// terminator instructions.
|
|
DEBUG({
|
|
dbgs() << "Hoisting " << *MI;
|
|
if (Preheader->getBasicBlock())
|
|
dbgs() << " to MachineBasicBlock "
|
|
<< Preheader->getName();
|
|
if (MI->getParent()->getBasicBlock())
|
|
dbgs() << " from MachineBasicBlock "
|
|
<< MI->getParent()->getName();
|
|
dbgs() << "\n";
|
|
});
|
|
|
|
// If this is the first instruction being hoisted to the preheader,
|
|
// initialize the CSE map with potential common expressions.
|
|
if (FirstInLoop) {
|
|
InitCSEMap(Preheader);
|
|
FirstInLoop = false;
|
|
}
|
|
|
|
// Look for opportunity to CSE the hoisted instruction.
|
|
unsigned Opcode = MI->getOpcode();
|
|
DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
|
|
CI = CSEMap.find(Opcode);
|
|
if (!EliminateCSE(MI, CI)) {
|
|
// Otherwise, splice the instruction to the preheader.
|
|
Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
|
|
|
|
// Update register pressure for BBs from header to this block.
|
|
UpdateBackTraceRegPressure(MI);
|
|
|
|
// Clear the kill flags of any register this instruction defines,
|
|
// since they may need to be live throughout the entire loop
|
|
// rather than just live for part of it.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isReg() && MO.isDef() && !MO.isDead())
|
|
MRI->clearKillFlags(MO.getReg());
|
|
}
|
|
|
|
// Add to the CSE map.
|
|
if (CI != CSEMap.end())
|
|
CI->second.push_back(MI);
|
|
else {
|
|
std::vector<const MachineInstr*> CSEMIs;
|
|
CSEMIs.push_back(MI);
|
|
CSEMap.insert(std::make_pair(Opcode, CSEMIs));
|
|
}
|
|
}
|
|
|
|
++NumHoisted;
|
|
Changed = true;
|
|
|
|
return true;
|
|
}
|
|
|
|
MachineBasicBlock *MachineLICM::getCurPreheader() {
|
|
// Determine the block to which to hoist instructions. If we can't find a
|
|
// suitable loop predecessor, we can't do any hoisting.
|
|
|
|
// If we've tried to get a preheader and failed, don't try again.
|
|
if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
|
|
return 0;
|
|
|
|
if (!CurPreheader) {
|
|
CurPreheader = CurLoop->getLoopPreheader();
|
|
if (!CurPreheader) {
|
|
MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
|
|
if (!Pred) {
|
|
CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
|
|
return 0;
|
|
}
|
|
|
|
CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
|
|
if (!CurPreheader) {
|
|
CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
|
|
return 0;
|
|
}
|
|
}
|
|
}
|
|
return CurPreheader;
|
|
}
|