llvm-6502/lib/Target/X86/Utils/X86ShuffleDecode.cpp
Bruno Cardoso Lopes 65b74e1d00 Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00

218 lines
7.1 KiB
C++

//===-- X86ShuffleDecode.cpp - X86 shuffle decode logic -------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Define several functions to decode x86 specific shuffle semantics into a
// generic vector mask.
//
//===----------------------------------------------------------------------===//
#include "X86ShuffleDecode.h"
//===----------------------------------------------------------------------===//
// Vector Mask Decoding
//===----------------------------------------------------------------------===//
namespace llvm {
void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) {
// Defaults the copying the dest value.
ShuffleMask.push_back(0);
ShuffleMask.push_back(1);
ShuffleMask.push_back(2);
ShuffleMask.push_back(3);
// Decode the immediate.
unsigned ZMask = Imm & 15;
unsigned CountD = (Imm >> 4) & 3;
unsigned CountS = (Imm >> 6) & 3;
// CountS selects which input element to use.
unsigned InVal = 4+CountS;
// CountD specifies which element of destination to update.
ShuffleMask[CountD] = InVal;
// ZMask zaps values, potentially overriding the CountD elt.
if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero;
if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero;
if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero;
if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero;
}
// <3,1> or <6,7,2,3>
void DecodeMOVHLPSMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
for (unsigned i = NElts/2; i != NElts; ++i)
ShuffleMask.push_back(NElts+i);
for (unsigned i = NElts/2; i != NElts; ++i)
ShuffleMask.push_back(i);
}
// <0,2> or <0,1,4,5>
void DecodeMOVLHPSMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
for (unsigned i = 0; i != NElts/2; ++i)
ShuffleMask.push_back(i);
for (unsigned i = 0; i != NElts/2; ++i)
ShuffleMask.push_back(NElts+i);
}
void DecodePSHUFMask(unsigned NElts, unsigned Imm,
SmallVectorImpl<unsigned> &ShuffleMask) {
for (unsigned i = 0; i != NElts; ++i) {
ShuffleMask.push_back(Imm % NElts);
Imm /= NElts;
}
}
void DecodePSHUFHWMask(unsigned Imm,
SmallVectorImpl<unsigned> &ShuffleMask) {
ShuffleMask.push_back(0);
ShuffleMask.push_back(1);
ShuffleMask.push_back(2);
ShuffleMask.push_back(3);
for (unsigned i = 0; i != 4; ++i) {
ShuffleMask.push_back(4+(Imm & 3));
Imm >>= 2;
}
}
void DecodePSHUFLWMask(unsigned Imm,
SmallVectorImpl<unsigned> &ShuffleMask) {
for (unsigned i = 0; i != 4; ++i) {
ShuffleMask.push_back((Imm & 3));
Imm >>= 2;
}
ShuffleMask.push_back(4);
ShuffleMask.push_back(5);
ShuffleMask.push_back(6);
ShuffleMask.push_back(7);
}
void DecodePUNPCKLBWMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i8, NElts), ShuffleMask);
}
void DecodePUNPCKLWDMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i16, NElts), ShuffleMask);
}
void DecodePUNPCKLDQMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i32, NElts), ShuffleMask);
}
void DecodePUNPCKLQDQMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask);
}
void DecodePUNPCKLMask(EVT VT,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeUNPCKLPMask(VT, ShuffleMask);
}
void DecodePUNPCKHMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
for (unsigned i = 0; i != NElts/2; ++i) {
ShuffleMask.push_back(i+NElts/2);
ShuffleMask.push_back(i+NElts+NElts/2);
}
}
void DecodeSHUFPSMask(unsigned NElts, unsigned Imm,
SmallVectorImpl<unsigned> &ShuffleMask) {
// Part that reads from dest.
for (unsigned i = 0; i != NElts/2; ++i) {
ShuffleMask.push_back(Imm % NElts);
Imm /= NElts;
}
// Part that reads from src.
for (unsigned i = 0; i != NElts/2; ++i) {
ShuffleMask.push_back(Imm % NElts + NElts);
Imm /= NElts;
}
}
void DecodeUNPCKHPMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
for (unsigned i = 0; i != NElts/2; ++i) {
ShuffleMask.push_back(i+NElts/2); // Reads from dest
ShuffleMask.push_back(i+NElts+NElts/2); // Reads from src
}
}
void DecodeUNPCKLPSMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i32, NElts), ShuffleMask);
}
void DecodeUNPCKLPDMask(unsigned NElts,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask);
}
/// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd
/// etc. VT indicates the type of the vector allowing it to handle different
/// datatypes and vector widths.
void DecodeUNPCKLPMask(EVT VT,
SmallVectorImpl<unsigned> &ShuffleMask) {
unsigned NumElts = VT.getVectorNumElements();
// Handle vector lengths > 128 bits. Define a "section" as a set of
// 128 bits. AVX defines UNPCK* to operate independently on 128-bit
// sections.
unsigned NumSections = VT.getSizeInBits() / 128;
if (NumSections == 0 ) NumSections = 1; // Handle MMX
unsigned NumSectionElts = NumElts / NumSections;
unsigned Start = 0;
unsigned End = NumSectionElts / 2;
for (unsigned s = 0; s < NumSections; ++s) {
for (unsigned i = Start; i != End; ++i) {
ShuffleMask.push_back(i); // Reads from dest/src1
ShuffleMask.push_back(i+NumSectionElts); // Reads from src/src2
}
// Process the next 128 bits.
Start += NumSectionElts;
End += NumSectionElts;
}
}
void DecodeVPERMILPSMask(unsigned NElts, unsigned Imm,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeVPERMILMask(MVT::getVectorVT(MVT::i32, NElts), Imm, ShuffleMask);
}
void DecodeVPERMILPDMask(unsigned NElts, unsigned Imm,
SmallVectorImpl<unsigned> &ShuffleMask) {
DecodeVPERMILMask(MVT::getVectorVT(MVT::i64, NElts), Imm, ShuffleMask);
}
// DecodeVPERMILMask - Decodes VPERMIL permutes for any 128-bit
// with 32/64-bit elements. For 256-bit vectors, it's considered
// as two 128 lanes and the mask of the first lane should be
// identical of the second one.
void DecodeVPERMILMask(EVT VT, unsigned Imm,
SmallVectorImpl<unsigned> &ShuffleMask) {
unsigned NumElts = VT.getVectorNumElements();
unsigned NumLanes = VT.getSizeInBits()/128;
for (unsigned l = 0; l != NumLanes; ++l) {
for (unsigned i = 0; i != NumElts/NumLanes; ++i) {
unsigned Idx = (Imm >> (i*2)) & 0x3 ;
ShuffleMask.push_back(Idx+(l*NumElts/NumLanes));
}
}
}
} // llvm namespace