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nodes. This doesn't currently have much impact the generated code, but it does produce simpler-looking SelectionDAGs, and consequently simpler-looking ScheduleDAGs, because there are fewer spurious dependencies. In particular, CopyValueToVirtualRegister now uses the entry node as the input chain dependency for new CopyToReg nodes instead of calling getRoot and depending on the most recent memory reference. Also, rename UnorderedChains to PendingExports and pull it up from being a local variable in SelectionDAGISel::BuildSelectionDAG to being a member variable of SelectionDAGISel, so that it doesn't have to be passed around to all the places that need it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48893 91177308-0d34-0410-b5e6-96231b3b80d8
201 lines
7.4 KiB
C++
201 lines
7.4 KiB
C++
//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAGISel class, which is used as the common
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// base class for SelectionDAG-based instruction selectors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#include "llvm/Pass.h"
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#include "llvm/Constant.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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class SelectionDAGLowering;
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class SDOperand;
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class MachineRegisterInfo;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class TargetLowering;
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class FunctionLoweringInfo;
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class HazardRecognizer;
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class CollectorMetadata;
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/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
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/// pattern-matching instruction selectors.
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class SelectionDAGISel : public FunctionPass {
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public:
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TargetLowering &TLI;
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MachineRegisterInfo *RegInfo;
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SelectionDAG *CurDAG;
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MachineBasicBlock *BB;
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AliasAnalysis *AA;
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std::vector<SDNode*> TopOrder;
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unsigned DAGSize;
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CollectorMetadata *GCI;
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static char ID;
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explicit SelectionDAGISel(TargetLowering &tli) :
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FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0), GCI(0) {}
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TargetLowering &getTargetLowering() { return TLI; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual bool runOnFunction(Function &Fn);
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unsigned MakeReg(MVT::ValueType VT);
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
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virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
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virtual void SelectRootInit() {
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DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
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}
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/// SelectInlineAsmMemoryOperand - Select the specified address as a target
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/// addressing mode, according to the specified constraint code. If this does
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/// not match or is not implemented, return true. The resultant operands
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/// (which will appear in the machine instruction) should be added to the
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/// OutOps vector.
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virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
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char ConstraintCode,
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std::vector<SDOperand> &OutOps,
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SelectionDAG &DAG) {
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return true;
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}
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/// CanBeFoldedBy - Returns true if the specific operand node N of U can be
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/// folded during instruction selection that starts at Root?
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virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
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return true;
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}
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/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
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/// to use for this target when scheduling the DAG.
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virtual HazardRecognizer *CreateTargetHazardRecognizer();
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/// CaseBlock - This structure is used to communicate between SDLowering and
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/// SDISel for the code generation of additional basic blocks needed by multi-
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/// case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me)
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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Value *CmpLHS, *CmpMHS, *CmpRHS;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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};
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struct JumpTable {
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
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MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
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/// Reg - the virtual register containing the index of the jump table entry
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//. to jump to.
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unsigned Reg;
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/// JTI - the JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// MBB - the MBB into which to emit the code for the indirect jump.
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MachineBasicBlock *MBB;
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/// Default - the MBB of the default bb, which is a successor of the range
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/// check MBB. This is when updating PHI nodes in successors.
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MachineBasicBlock *Default;
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};
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struct JumpTableHeader {
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JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
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bool E = false):
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First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
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uint64_t First;
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uint64_t Last;
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Value *SValue;
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MachineBasicBlock *HeaderBB;
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bool Emitted;
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};
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typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
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struct BitTestCase {
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BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
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Mask(M), ThisBB(T), TargetBB(Tr) { }
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uint64_t Mask;
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MachineBasicBlock* ThisBB;
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MachineBasicBlock* TargetBB;
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};
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typedef SmallVector<BitTestCase, 3> BitTestInfo;
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struct BitTestBlock {
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BitTestBlock(uint64_t F, uint64_t R, Value* SV,
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unsigned Rg, bool E,
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MachineBasicBlock* P, MachineBasicBlock* D,
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const BitTestInfo& C):
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First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
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Parent(P), Default(D), Cases(C) { }
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uint64_t First;
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uint64_t Range;
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Value *SValue;
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unsigned Reg;
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bool Emitted;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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BitTestInfo Cases;
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};
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protected:
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/// Pick a safe ordering and emit instructions for each target node in the
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/// graph.
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void ScheduleAndEmitDAG(SelectionDAG &DAG);
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/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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/// by tblgen. Others should not call it.
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void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
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SelectionDAG &DAG);
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// Calls to these predicates are generated by tblgen.
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bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
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int64_t DesiredMaskS) const;
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bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
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int64_t DesiredMaskS) const;
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private:
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void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
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FunctionLoweringInfo &FuncInfo);
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void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
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std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
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FunctionLoweringInfo &FuncInfo);
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void CodeGenAndEmitDAG(SelectionDAG &DAG);
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void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
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/// SwitchCases - Vector of CaseBlock structures used to communicate
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/// SwitchInst code generation information.
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std::vector<CaseBlock> SwitchCases;
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/// JTCases - Vector of JumpTable structures which holds necessary information
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/// for emitting a jump tables during SwitchInst code generation.
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std::vector<JumpTableBlock> JTCases;
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std::vector<BitTestBlock> BitTestCases;
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};
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}
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#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
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