mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 22:29:56 +00:00
61bc72e9ae
Most of these are no longer used any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210915 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
2.4 KiB
C++
68 lines
2.4 KiB
C++
//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief Interface definition for SIRegisterInfo
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
#ifndef SIREGISTERINFO_H_
|
|
#define SIREGISTERINFO_H_
|
|
|
|
#include "AMDGPURegisterInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
struct SIRegisterInfo : public AMDGPURegisterInfo {
|
|
|
|
SIRegisterInfo(const AMDGPUSubtarget &st);
|
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
|
|
|
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
|
MachineFunction &MF) const override;
|
|
|
|
/// \brief get the register class of the specified type to use in the
|
|
/// CFGStructurizer
|
|
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
|
|
|
|
unsigned getHWRegIndex(unsigned Reg) const override;
|
|
|
|
/// \brief Return the 'base' register class for this register.
|
|
/// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
|
|
const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
|
|
|
|
/// \returns true if this class contains only SGPR registers
|
|
bool isSGPRClass(const TargetRegisterClass *RC) const;
|
|
|
|
/// \returns true if this class contains VGPR registers.
|
|
bool hasVGPRs(const TargetRegisterClass *RC) const;
|
|
|
|
/// \returns A VGPR reg class with the same width as \p SRC
|
|
const TargetRegisterClass *getEquivalentVGPRClass(
|
|
const TargetRegisterClass *SRC) const;
|
|
|
|
/// \returns The register class that is used for a sub-register of \p RC for
|
|
/// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
|
|
/// be returned.
|
|
const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
|
|
unsigned SubIdx) const;
|
|
|
|
/// \p Channel This is the register channel (e.g. a value from 0-16), not the
|
|
/// SubReg index.
|
|
/// \returns The sub-register of Reg that is in Channel.
|
|
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
|
|
unsigned Channel) const;
|
|
};
|
|
|
|
} // End namespace llvm
|
|
|
|
#endif // SIREGISTERINFO_H_
|