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MO_JumpTableIndex and MO_ExternalSymbol don't show up on inline asm. Keeping parts of the old asm printer just to print inline asm to a string that we then parse back looks like a hack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196111 91177308-0d34-0410-b5e6-96231b3b80d8
700 lines
24 KiB
C++
700 lines
24 KiB
C++
//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MIPS assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-asm-printer"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips.h"
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#include "MipsAsmPrinter.h"
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#include "MipsInstrInfo.h"
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#include "MipsMCInstLower.h"
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#include "MipsTargetStreamer.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
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return static_cast<MipsTargetStreamer &>(OutStreamer.getTargetStreamer());
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}
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bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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// Initialize TargetLoweringObjectFile.
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if (Subtarget->allowMixed16_32())
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const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
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.Initialize(OutContext, TM);
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MipsFI = MF.getInfo<MipsFunctionInfo>();
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MCP = MF.getConstantPool();
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AsmPrinter::runOnMachineFunction(MF);
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return true;
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}
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bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
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MCOp = MCInstLowering.LowerOperand(MO);
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return MCOp.isValid();
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}
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#include "MipsGenMCPseudoLowering.inc"
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void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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if (MI->isDebugValue()) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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PrintDebugValueComment(MI, OS);
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return;
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}
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// If we just ended a constant pool, mark it as such.
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if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
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OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
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InConstantPool = false;
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}
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if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
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// CONSTPOOL_ENTRY - This instruction represents a floating
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//constant pool in the function. The first operand is the ID#
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// for this instruction, the second is the index into the
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// MachineConstantPool that this is, the third is the size in
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// bytes of this constant pool entry.
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// The required alignment is specified on the basic block holding this MI.
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//
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unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
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unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
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// If this is the first entry of the pool, mark it.
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if (!InConstantPool) {
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OutStreamer.EmitDataRegion(MCDR_DataRegion);
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InConstantPool = true;
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}
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OutStreamer.EmitLabel(GetCPISymbol(LabelId));
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const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
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if (MCPE.isMachineConstantPoolEntry())
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EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
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else
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EmitGlobalConstant(MCPE.Val.ConstVal);
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return;
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}
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MachineBasicBlock::const_instr_iterator I = MI;
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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// Do any auto-generated pseudo lowerings.
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if (emitPseudoExpansionLowering(OutStreamer, &*I))
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continue;
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// The inMips16Mode() test is not permanent.
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// Some instructions are marked as pseudo right now which
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// would make the test fail for the wrong reason but
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// that will be fixed soon. We need this here because we are
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// removing another test for this situation downstream in the
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// callchain.
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//
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if (I->isPseudo() && !Subtarget->inMips16Mode())
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llvm_unreachable("Pseudo opcode found in EmitInstruction()");
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MCInst TmpInst0;
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MCInstLowering.Lower(I, TmpInst0);
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OutStreamer.EmitInstruction(TmpInst0);
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} while ((++I != E) && I->isInsideBundle()); // Delay slot check
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}
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//===----------------------------------------------------------------------===//
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//
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// Mips Asm Directives
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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// -- Mask directives "(f)mask bitmask, offset"
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// Tells the assembler which registers are saved and where.
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// assembler knows the register 31 (RA) is saved at prologue.
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// offset - the position before stack pointer subtraction indicating where
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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//
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// .frame $fp,48,$ra
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// .mask 0xc0000000,-8
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// addiu $sp, $sp, -48
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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//
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mask directives
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//===----------------------------------------------------------------------===//
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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// registers. For CPU registers consider RA, GP and FP for saving if necessary.
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void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
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// CPU and FPU Saved Registers Bitmasks
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unsigned CPUBitmask = 0, FPUBitmask = 0;
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int CPUTopSavedRegOff, FPUTopSavedRegOff;
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// Set the CPU and FPU Bitmasks
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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// size of stack area to which FP callee-saved regs are saved.
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unsigned CPURegSize = Mips::GPR32RegClass.getSize();
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unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
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unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
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bool HasAFGR64Reg = false;
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unsigned CSFPRegsSize = 0;
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unsigned i, e = CSI.size();
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// Set FPU Bitmask.
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for (i = 0; i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (Mips::GPR32RegClass.contains(Reg))
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break;
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unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
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if (Mips::AFGR64RegClass.contains(Reg)) {
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FPUBitmask |= (3 << RegNum);
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CSFPRegsSize += AFGR64RegSize;
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HasAFGR64Reg = true;
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continue;
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}
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FPUBitmask |= (1 << RegNum);
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CSFPRegsSize += FGR32RegSize;
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}
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// Set CPU Bitmask.
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for (; i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
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CPUBitmask |= (1 << RegNum);
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}
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// FP Regs are saved right below where the virtual frame pointer points to.
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FPUTopSavedRegOff = FPUBitmask ?
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(HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
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// CPU Regs are saved below FP Regs.
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CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
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// Print CPUBitmask
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O << "\t.mask \t"; printHex32(CPUBitmask, O);
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O << ',' << CPUTopSavedRegOff << '\n';
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// Print FPUBitmask
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O << "\t.fmask\t"; printHex32(FPUBitmask, O);
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O << "," << FPUTopSavedRegOff << '\n';
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}
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// Print a 32 bit hex number with all numbers.
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void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
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O << "0x";
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for (int i = 7; i >= 0; i--)
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O.write_hex((Value & (0xF << (i*4))) >> (i*4));
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}
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//===----------------------------------------------------------------------===//
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// Frame and Set directives
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//===----------------------------------------------------------------------===//
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/// Frame Directive
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void MipsAsmPrinter::emitFrameDirective() {
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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unsigned stackReg = RI.getFrameRegister(*MF);
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unsigned returnReg = RI.getRARegister();
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unsigned stackSize = MF->getFrameInfo()->getStackSize();
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if (OutStreamer.hasRawTextSupport())
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OutStreamer.EmitRawText("\t.frame\t$" +
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StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
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"," + Twine(stackSize) + ",$" +
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StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
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}
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/// Emit Set directives.
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const char *MipsAsmPrinter::getCurrentABIString() const {
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switch (Subtarget->getTargetABI()) {
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case MipsSubtarget::O32: return "abi32";
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case MipsSubtarget::N32: return "abiN32";
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case MipsSubtarget::N64: return "abi64";
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case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
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default: llvm_unreachable("Unknown Mips ABI");
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}
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}
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void MipsAsmPrinter::EmitFunctionEntryLabel() {
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if (OutStreamer.hasRawTextSupport()) {
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if (Subtarget->inMips16Mode())
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OutStreamer.EmitRawText(StringRef("\t.set\tmips16"));
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else
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OutStreamer.EmitRawText(StringRef("\t.set\tnomips16"));
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// leave out until FSF available gas has micromips changes
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// OutStreamer.EmitRawText(StringRef("\t.set\tnomicromips"));
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OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
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}
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if (Subtarget->inMicroMipsMode())
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getTargetStreamer().emitMipsHackSTOCG(CurrentFnSym,
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(unsigned)ELF::STO_MIPS_MICROMIPS);
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OutStreamer.EmitLabel(CurrentFnSym);
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}
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/// EmitFunctionBodyStart - Targets can override this to emit stuff before
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/// the first basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyStart() {
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MCInstLowering.Initialize(&MF->getContext());
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bool IsNakedFunction =
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MF->getFunction()->
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getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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Attribute::Naked);
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if (!IsNakedFunction)
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emitFrameDirective();
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if (OutStreamer.hasRawTextSupport()) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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if (!IsNakedFunction)
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printSavedRegsBitmask(OS);
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OutStreamer.EmitRawText(OS.str());
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if (!Subtarget->inMips16Mode()) {
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OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
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OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
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OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
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}
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}
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}
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/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
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/// the last basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyEnd() {
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// There are instruction for this macros, but they must
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// always be at the function end, and we can't emit and
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// break with BB logic.
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if (OutStreamer.hasRawTextSupport()) {
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if (!Subtarget->inMips16Mode()) {
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OutStreamer.EmitRawText(StringRef("\t.set\tat"));
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OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
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OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
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}
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OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
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}
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// Make sure to terminate any constant pools that were at the end
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// of the function.
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if (!InConstantPool)
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return;
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InConstantPool = false;
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OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
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}
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/// isBlockOnlyReachableByFallthough - Return true if the basic block has
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/// exactly one predecessor and the control transfer mechanism between
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/// the predecessor and this block is a fall-through.
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bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
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MBB) const {
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// The predecessor has to be immediately before this block.
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const MachineBasicBlock *Pred = *MBB->pred_begin();
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// If the predecessor is a switch statement, assume a jump table
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// implementation, so it is not a fall through.
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if (const BasicBlock *bb = Pred->getBasicBlock())
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if (isa<SwitchInst>(bb->getTerminator()))
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return false;
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// If this is a landing pad, it isn't a fall through. If it has no preds,
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// then nothing falls through to it.
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if (MBB->isLandingPad() || MBB->pred_empty())
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return false;
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// If there isn't exactly one predecessor, it can't be a fall through.
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MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
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++PI2;
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if (PI2 != MBB->pred_end())
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return false;
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// The predecessor has to be immediately before this block.
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if (!Pred->isLayoutSuccessor(MBB))
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return false;
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// If the block is completely empty, then it definitely does fall through.
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if (Pred->empty())
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return true;
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// Otherwise, check the last instruction.
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// Check if the last terminator is an unconditional branch.
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MachineBasicBlock::const_iterator I = Pred->end();
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while (I != Pred->begin() && !(--I)->isTerminator()) ;
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return !I->isBarrier();
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}
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// Print out an operand for an inline asm expression.
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bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant,const char *ExtraCode,
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raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0) return true; // Unknown modifier.
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (ExtraCode[0]) {
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default:
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// See if this is a generic print operand
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return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
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case 'X': // hex const int
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if ((MO.getType()) != MachineOperand::MO_Immediate)
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return true;
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O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
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return false;
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case 'x': // hex const int (low 16 bits)
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if ((MO.getType()) != MachineOperand::MO_Immediate)
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return true;
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O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
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return false;
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case 'd': // decimal const int
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if ((MO.getType()) != MachineOperand::MO_Immediate)
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return true;
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O << MO.getImm();
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return false;
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case 'm': // decimal const int minus 1
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if ((MO.getType()) != MachineOperand::MO_Immediate)
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return true;
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O << MO.getImm() - 1;
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return false;
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case 'z': {
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// $0 if zero, regular printing otherwise
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if (MO.getType() != MachineOperand::MO_Immediate)
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return true;
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int64_t Val = MO.getImm();
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if (Val)
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O << Val;
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else
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O << "$0";
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return false;
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}
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case 'D': // Second part of a double word register operand
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case 'L': // Low order register of a double word register operand
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case 'M': // High order register of a double word register operand
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{
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if (OpNum == 0)
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return true;
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const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
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if (!FlagsOP.isImm())
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return true;
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unsigned Flags = FlagsOP.getImm();
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unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
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// Number of registers represented by this operand. We are looking
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// for 2 for 32 bit mode and 1 for 64 bit mode.
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if (NumVals != 2) {
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if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
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unsigned Reg = MO.getReg();
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O << '$' << MipsInstPrinter::getRegisterName(Reg);
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return false;
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}
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return true;
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}
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unsigned RegOp = OpNum;
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if (!Subtarget->isGP64bit()){
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// Endianess reverses which register holds the high or low value
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// between M and L.
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switch(ExtraCode[0]) {
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case 'M':
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RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
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break;
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case 'L':
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RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
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break;
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case 'D': // Always the second part
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RegOp = OpNum + 1;
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}
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if (RegOp >= MI->getNumOperands())
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return true;
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const MachineOperand &MO = MI->getOperand(RegOp);
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if (!MO.isReg())
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return true;
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unsigned Reg = MO.getReg();
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O << '$' << MipsInstPrinter::getRegisterName(Reg);
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return false;
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}
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}
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case 'w':
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|
// Print MSA registers for the 'f' constraint
|
|
// In LLVM, the 'w' modifier doesn't need to do anything.
|
|
// We can just call printOperand as normal.
|
|
break;
|
|
}
|
|
}
|
|
|
|
printOperand(MI, OpNum, O);
|
|
return false;
|
|
}
|
|
|
|
bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
|
unsigned OpNum, unsigned AsmVariant,
|
|
const char *ExtraCode,
|
|
raw_ostream &O) {
|
|
int Offset = 0;
|
|
// Currently we are expecting either no ExtraCode or 'D'
|
|
if (ExtraCode) {
|
|
if (ExtraCode[0] == 'D')
|
|
Offset = 4;
|
|
else
|
|
return true; // Unknown modifier.
|
|
}
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
assert(MO.isReg() && "unexpected inline asm memory operand");
|
|
O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
|
|
|
|
return false;
|
|
}
|
|
|
|
void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
|
|
raw_ostream &O) {
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
bool closeP = false;
|
|
|
|
if (MO.getTargetFlags())
|
|
closeP = true;
|
|
|
|
switch(MO.getTargetFlags()) {
|
|
case MipsII::MO_GPREL: O << "%gp_rel("; break;
|
|
case MipsII::MO_GOT_CALL: O << "%call16("; break;
|
|
case MipsII::MO_GOT: O << "%got("; break;
|
|
case MipsII::MO_ABS_HI: O << "%hi("; break;
|
|
case MipsII::MO_ABS_LO: O << "%lo("; break;
|
|
case MipsII::MO_TLSGD: O << "%tlsgd("; break;
|
|
case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
|
|
case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
|
|
case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
|
|
case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
|
|
case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
|
|
case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
|
|
case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
|
|
case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
|
|
}
|
|
|
|
switch (MO.getType()) {
|
|
case MachineOperand::MO_Register:
|
|
O << '$'
|
|
<< StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
|
|
break;
|
|
|
|
case MachineOperand::MO_Immediate:
|
|
O << MO.getImm();
|
|
break;
|
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
O << *MO.getMBB()->getSymbol();
|
|
return;
|
|
|
|
case MachineOperand::MO_GlobalAddress:
|
|
O << *getSymbol(MO.getGlobal());
|
|
break;
|
|
|
|
case MachineOperand::MO_BlockAddress: {
|
|
MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
|
|
O << BA->getName();
|
|
break;
|
|
}
|
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
|
O << MAI->getPrivateGlobalPrefix() << "CPI"
|
|
<< getFunctionNumber() << "_" << MO.getIndex();
|
|
if (MO.getOffset())
|
|
O << "+" << MO.getOffset();
|
|
break;
|
|
|
|
default:
|
|
llvm_unreachable("<unknown operand type>");
|
|
}
|
|
|
|
if (closeP) O << ")";
|
|
}
|
|
|
|
void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
|
|
raw_ostream &O) {
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
if (MO.isImm())
|
|
O << (unsigned short int)MO.getImm();
|
|
else
|
|
printOperand(MI, opNum, O);
|
|
}
|
|
|
|
void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
|
|
raw_ostream &O) {
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
if (MO.isImm())
|
|
O << (unsigned short int)(unsigned char)MO.getImm();
|
|
else
|
|
printOperand(MI, opNum, O);
|
|
}
|
|
|
|
void MipsAsmPrinter::
|
|
printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
|
// Load/Store memory operands -- imm($reg)
|
|
// If PIC target the target is loaded as the
|
|
// pattern lw $25,%call16($28)
|
|
printOperand(MI, opNum+1, O);
|
|
O << "(";
|
|
printOperand(MI, opNum, O);
|
|
O << ")";
|
|
}
|
|
|
|
void MipsAsmPrinter::
|
|
printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
|
// when using stack locations for not load/store instructions
|
|
// print the same way as all normal 3 operand instructions.
|
|
printOperand(MI, opNum, O);
|
|
O << ", ";
|
|
printOperand(MI, opNum+1, O);
|
|
return;
|
|
}
|
|
|
|
void MipsAsmPrinter::
|
|
printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
|
|
const char *Modifier) {
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
|
|
// FIXME: Use SwitchSection.
|
|
|
|
// TODO: Need to add -mabicalls and -mno-abicalls flags.
|
|
// Currently we assume that -mabicalls is the default.
|
|
if (OutStreamer.hasRawTextSupport()) {
|
|
OutStreamer.EmitRawText(StringRef("\t.abicalls"));
|
|
Reloc::Model RM = Subtarget->getRelocationModel();
|
|
if (RM == Reloc::Static && !Subtarget->hasMips64())
|
|
OutStreamer.EmitRawText(StringRef("\t.option\tpic0"));
|
|
}
|
|
|
|
// Tell the assembler which ABI we are using
|
|
if (OutStreamer.hasRawTextSupport())
|
|
OutStreamer.EmitRawText("\t.section .mdebug." +
|
|
Twine(getCurrentABIString()));
|
|
|
|
// TODO: handle O64 ABI
|
|
if (OutStreamer.hasRawTextSupport()) {
|
|
if (Subtarget->isABI_EABI()) {
|
|
if (Subtarget->isGP32bit())
|
|
OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
|
|
else
|
|
OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
|
|
}
|
|
}
|
|
|
|
// return to previous section
|
|
if (OutStreamer.hasRawTextSupport())
|
|
OutStreamer.EmitRawText(StringRef("\t.previous"));
|
|
|
|
}
|
|
|
|
static void emitELFHeaderFlagsCG(MipsTargetStreamer &TargetStreamer,
|
|
const MipsSubtarget &Subtarget) {
|
|
// Update e_header flags
|
|
unsigned EFlags = 0;
|
|
|
|
// TODO: Need to add -mabicalls and -mno-abicalls flags.
|
|
// Currently we assume that -mabicalls is the default.
|
|
EFlags |= ELF::EF_MIPS_CPIC;
|
|
|
|
if (Subtarget.inMips16Mode())
|
|
EFlags |= ELF::EF_MIPS_ARCH_ASE_M16;
|
|
else
|
|
EFlags |= ELF::EF_MIPS_NOREORDER;
|
|
|
|
// Architecture
|
|
if (Subtarget.hasMips64r2())
|
|
EFlags |= ELF::EF_MIPS_ARCH_64R2;
|
|
else if (Subtarget.hasMips64())
|
|
EFlags |= ELF::EF_MIPS_ARCH_64;
|
|
else if (Subtarget.hasMips32r2())
|
|
EFlags |= ELF::EF_MIPS_ARCH_32R2;
|
|
else
|
|
EFlags |= ELF::EF_MIPS_ARCH_32;
|
|
|
|
if (Subtarget.inMicroMipsMode())
|
|
EFlags |= ELF::EF_MIPS_MICROMIPS;
|
|
|
|
// ABI
|
|
if (Subtarget.isABI_O32())
|
|
EFlags |= ELF::EF_MIPS_ABI_O32;
|
|
|
|
// Relocation Model
|
|
Reloc::Model RM = Subtarget.getRelocationModel();
|
|
if (RM == Reloc::PIC_ || RM == Reloc::Default)
|
|
EFlags |= ELF::EF_MIPS_PIC;
|
|
else if (RM == Reloc::Static)
|
|
; // Do nothing for Reloc::Static
|
|
else
|
|
llvm_unreachable("Unsupported relocation model for e_flags");
|
|
|
|
TargetStreamer.emitMipsHackELFFlags(EFlags);
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
|
// Emit Mips ELF register info
|
|
Subtarget->getMReginfo().emitMipsReginfoSectionCG(
|
|
OutStreamer, getObjFileLowering(), *Subtarget);
|
|
emitELFHeaderFlagsCG(getTargetStreamer(), *Subtarget);
|
|
}
|
|
|
|
void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
|
|
raw_ostream &OS) {
|
|
// TODO: implement
|
|
}
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeMipsAsmPrinter() {
|
|
RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
|
|
RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
|
|
RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
|
|
RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
|
|
}
|