mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-10 17:07:06 +00:00
061efcfb3e
Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
3.6 KiB
C++
98 lines
3.6 KiB
C++
//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "Sparc.h"
|
|
#include "SparcTargetMachine.h"
|
|
#include "llvm/PassManager.h"
|
|
#include "llvm/CodeGen/Passes.h"
|
|
#include "llvm/Support/TargetRegistry.h"
|
|
using namespace llvm;
|
|
|
|
extern "C" void LLVMInitializeSparcTarget() {
|
|
// Register the target.
|
|
RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
|
|
RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
|
|
}
|
|
|
|
/// SparcTargetMachine ctor - Create an ILP32 architecture model
|
|
///
|
|
SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
|
|
StringRef CPU, StringRef FS,
|
|
const TargetOptions &Options,
|
|
Reloc::Model RM, CodeModel::Model CM,
|
|
CodeGenOpt::Level OL,
|
|
bool is64bit)
|
|
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
|
|
Subtarget(TT, CPU, FS, is64bit),
|
|
DataLayout(Subtarget.getDataLayout()),
|
|
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
|
|
FrameLowering(Subtarget) {
|
|
}
|
|
|
|
namespace {
|
|
/// Sparc Code Generator Pass Configuration Options.
|
|
class SparcPassConfig : public TargetPassConfig {
|
|
public:
|
|
SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
|
|
: TargetPassConfig(TM, PM) {}
|
|
|
|
SparcTargetMachine &getSparcTargetMachine() const {
|
|
return getTM<SparcTargetMachine>();
|
|
}
|
|
|
|
virtual bool addInstSelector();
|
|
virtual bool addPreEmitPass();
|
|
};
|
|
} // namespace
|
|
|
|
TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
return new SparcPassConfig(this, PM);
|
|
}
|
|
|
|
bool SparcPassConfig::addInstSelector() {
|
|
PM.add(createSparcISelDag(getSparcTargetMachine()));
|
|
return false;
|
|
}
|
|
|
|
/// addPreEmitPass - This pass may be implemented by targets that want to run
|
|
/// passes immediately before machine code is emitted. This should return
|
|
/// true if -print-machineinstrs should print out the code after the passes.
|
|
bool SparcPassConfig::addPreEmitPass(){
|
|
PM.add(createSparcFPMoverPass(getSparcTargetMachine()));
|
|
PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
|
|
return true;
|
|
}
|
|
|
|
void SparcV8TargetMachine::anchor() { }
|
|
|
|
SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
|
|
StringRef TT, StringRef CPU,
|
|
StringRef FS,
|
|
const TargetOptions &Options,
|
|
Reloc::Model RM,
|
|
CodeModel::Model CM,
|
|
CodeGenOpt::Level OL)
|
|
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
|
|
}
|
|
|
|
void SparcV9TargetMachine::anchor() { }
|
|
|
|
SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
|
|
StringRef TT, StringRef CPU,
|
|
StringRef FS,
|
|
const TargetOptions &Options,
|
|
Reloc::Model RM,
|
|
CodeModel::Model CM,
|
|
CodeGenOpt::Level OL)
|
|
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
|
}
|