llvm-6502/test/CodeGen/PowerPC/itofp128.ll
Dan Gohman ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00

15 lines
699 B
LLVM

; RUN: llvm-as < %s | llc -march=ppc64
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc64-apple-darwin9.2.0"
define i128 @__fixunstfti(ppc_fp128 %a) nounwind {
entry:
%tmp1213 = uitofp i128 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
%tmp15 = fsub ppc_fp128 %a, %tmp1213 ; <ppc_fp128> [#uses=1]
%tmp2829 = fptoui ppc_fp128 %tmp15 to i64 ; <i64> [#uses=1]
%tmp282930 = zext i64 %tmp2829 to i128 ; <i128> [#uses=1]
%tmp32 = add i128 %tmp282930, 0 ; <i128> [#uses=1]
ret i128 %tmp32
}