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https://github.com/c64scene-ar/llvm-6502.git
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f07fc974d3
of different register classes. e.g. %reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3 Where %reg1048 is a GR32 register. This is not impossible to handle, but it is pretty hard and very rare. This should unbreak the dragonegg builder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102672 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
4.6 KiB
LLVM
143 lines
4.6 KiB
LLVM
; RUN: llc < %s -relocation-model=pic -disable-fp-elim -verify-machineinstrs
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-unknown-linux-gnu"
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define void @_ZN12_GLOBAL__N_113SPUAsmPrinter15EmitInstructionEPKN4llvm12MachineInstrE(i8* %this, i8* %MI) nounwind inlinehint align 2 {
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entry:
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br i1 undef, label %"3.i", label %"4.i"
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"3.i": ; preds = %entry
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unreachable
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"4.i": ; preds = %entry
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switch i32 undef, label %_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit [
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i32 1, label %"5.i"
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i32 2, label %"6.i"
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i32 3, label %"7.i"
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i32 4, label %"8.i"
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i32 5, label %"9.i"
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]
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"5.i": ; preds = %"4.i"
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unreachable
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"6.i": ; preds = %"4.i"
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switch i32 undef, label %"11.i" [
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i32 1, label %"12.i"
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i32 2, label %"13.i"
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i32 3, label %_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit
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i32 4, label %"14.i"
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]
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"7.i": ; preds = %"4.i"
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unreachable
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"8.i": ; preds = %"4.i"
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unreachable
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"9.i": ; preds = %"4.i"
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unreachable
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"11.i": ; preds = %"6.i"
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switch i32 undef, label %"15.i" [
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i32 1, label %"16.i"
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i32 2, label %"17.i"
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i32 3, label %"18.i"
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i32 4, label %"19.i"
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i32 5, label %"20.i"
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i32 6, label %"21.i"
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i32 7, label %"24.i"
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i32 8, label %"27.i"
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i32 9, label %"28.i"
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i32 10, label %"29.i"
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i32 11, label %"30.i"
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i32 12, label %"31.i"
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i32 13, label %"32.i"
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i32 14, label %"39.i"
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]
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"12.i": ; preds = %"6.i"
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unreachable
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"13.i": ; preds = %"6.i"
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unreachable
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"14.i": ; preds = %"6.i"
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unreachable
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"15.i": ; preds = %"11.i"
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unreachable
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"16.i": ; preds = %"11.i"
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unreachable
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"17.i": ; preds = %"11.i"
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unreachable
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"18.i": ; preds = %"11.i"
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unreachable
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"19.i": ; preds = %"11.i"
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unreachable
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"20.i": ; preds = %"11.i"
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unreachable
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"21.i": ; preds = %"11.i"
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br i1 undef, label %"22.i", label %"23.i"
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"22.i": ; preds = %"21.i"
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unreachable
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"23.i": ; preds = %"21.i"
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unreachable
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"24.i": ; preds = %"11.i"
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unreachable
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"27.i": ; preds = %"11.i"
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unreachable
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"28.i": ; preds = %"11.i"
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unreachable
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"29.i": ; preds = %"11.i"
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unreachable
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"30.i": ; preds = %"11.i"
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unreachable
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"31.i": ; preds = %"11.i"
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unreachable
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"32.i": ; preds = %"11.i"
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unreachable
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"39.i": ; preds = %"11.i"
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br i1 undef, label %"41.i", label %"40.i"
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"40.i": ; preds = %"39.i"
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unreachable
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"41.i": ; preds = %"39.i"
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%0 = call i64 @_ZNK4llvm14MachineOperand6getImmEv(i8 undef) nounwind inlinehint ; <i64> [#uses=1]
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%1 = trunc i64 %0 to i16 ; <i16> [#uses=1]
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br i1 undef, label %"42.i", label %"43.i"
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"42.i": ; preds = %"41.i"
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unreachable
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"43.i": ; preds = %"41.i"
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%2 = and i16 %1, -16 ; <i16> [#uses=1]
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%3 = sext i16 %2 to i64 ; <i64> [#uses=1]
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%4 = call i8 @_ZN4llvm11raw_ostreamlsEl(i8 undef, i64 %3) nounwind ; <i8> [#uses=0]
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unreachable
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_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit: ; preds = %"6.i", %"4.i"
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ret void
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}
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declare i64 @_ZNK4llvm14MachineOperand6getImmEv(i8) nounwind inlinehint align 2
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declare i8 @_ZN4llvm11raw_ostreamlsEl(i8, i64)
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