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https://github.com/c64scene-ar/llvm-6502.git
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a140448780
This should expose more of the actually used VALU instructions to the machine optimization passes. This also should help getting i1 handling into a better state. For not entirly understood reasons, this fixes the split-scalar-i64-add.ll test where a 64-bit add would only partially be moved to the VALU resulting in use of undefined VCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222256 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
879 B
LLVM
30 lines
879 B
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}br_i1_phi:
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
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; SI: s_and_saveexec_b64
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; SI: s_xor_b64
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; SI: v_mov_b32_e32 [[REG]], -1{{$}}
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; SI: v_cmp_ne_i32_e64 {{s\[[0-9]+:[0-9]+\]}}, [[REG]], 0
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; SI: s_and_saveexec_b64
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; SI: s_xor_b64
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; SI: s_endpgm
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define void @br_i1_phi(i32 %arg, i1 %arg1) #0 {
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bb:
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br i1 %arg1, label %bb2, label %bb3
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bb2: ; preds = %bb
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br label %bb3
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bb3: ; preds = %bb2, %bb
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%tmp = phi i1 [ true, %bb2 ], [ false, %bb ]
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br i1 %tmp, label %bb4, label %bb6
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bb4: ; preds = %bb3
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%tmp5 = mul i32 undef, %arg
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br label %bb6
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bb6: ; preds = %bb4, %bb3
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ret void
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}
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