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2f69e4cf32
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
assert(!MI->isTerminator() && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
434 B
LLVM
18 lines
434 B
LLVM
; RUN: true
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; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; CHECK: vaddh(r{{[0-9]+}}, r{{[0-9]+}})
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@j = external global i32
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@k = external global i32
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define void @foo() nounwind {
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entry:
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%0 = load i32* @j, align 4
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%1 = load i32* @k, align 4
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%2 = call i32 @llvm.hexagon.A2.svaddh(i32 %0, i32 %1)
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store i32 %2, i32* @k, align 4
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ret void
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}
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declare i32 @llvm.hexagon.A2.svaddh(i32, i32) nounwind readnone
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