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This merges the behavior of splitSingleBlocks into splitAroundRegion, so the RS_Region and RS_Block register stages can be coalesced. That means the leftover intervals after region splitting go directly to spilling instead of a second pass of per-block splitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129379 91177308-0d34-0410-b5e6-96231b3b80d8
966 lines
33 KiB
C++
966 lines
33 KiB
C++
//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SplitAnalysis class as well as mutator functions for
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// live range splitting.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "SplitKit.h"
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#include "LiveRangeEdit.h"
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#include "VirtRegMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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STATISTIC(NumFinished, "Number of splits finished");
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STATISTIC(NumSimple, "Number of splits that were simple");
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//===----------------------------------------------------------------------===//
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// Split Analysis
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//===----------------------------------------------------------------------===//
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SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
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const LiveIntervals &lis,
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const MachineLoopInfo &mli)
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: MF(vrm.getMachineFunction()),
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VRM(vrm),
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LIS(lis),
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Loops(mli),
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TII(*MF.getTarget().getInstrInfo()),
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CurLI(0),
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LastSplitPoint(MF.getNumBlockIDs()) {}
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void SplitAnalysis::clear() {
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UseSlots.clear();
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UseBlocks.clear();
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ThroughBlocks.clear();
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CurLI = 0;
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}
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SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
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const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
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const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
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std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
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// Compute split points on the first call. The pair is independent of the
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// current live interval.
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if (!LSP.first.isValid()) {
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MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
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if (FirstTerm == MBB->end())
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LSP.first = LIS.getMBBEndIdx(MBB);
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else
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LSP.first = LIS.getInstructionIndex(FirstTerm);
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// If there is a landing pad successor, also find the call instruction.
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if (!LPad)
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return LSP.first;
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// There may not be a call instruction (?) in which case we ignore LPad.
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LSP.second = LSP.first;
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for (MachineBasicBlock::const_iterator I = FirstTerm, E = MBB->begin();
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I != E; --I)
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if (I->getDesc().isCall()) {
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LSP.second = LIS.getInstructionIndex(I);
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break;
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}
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}
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// If CurLI is live into a landing pad successor, move the last split point
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// back to the call that may throw.
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if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
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return LSP.second;
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else
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return LSP.first;
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}
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/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
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void SplitAnalysis::analyzeUses() {
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assert(UseSlots.empty() && "Call clear first");
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// First get all the defs from the interval values. This provides the correct
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// slots for early clobbers.
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for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
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E = CurLI->vni_end(); I != E; ++I)
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if (!(*I)->isPHIDef() && !(*I)->isUnused())
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UseSlots.push_back((*I)->def);
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// Get use slots form the use-def chain.
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (MachineRegisterInfo::use_nodbg_iterator
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I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
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++I)
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if (!I.getOperand().isUndef())
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UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
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array_pod_sort(UseSlots.begin(), UseSlots.end());
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// Remove duplicates, keeping the smaller slot for each instruction.
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// That is what we want for early clobbers.
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UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
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SlotIndex::isSameInstr),
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UseSlots.end());
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// Compute per-live block info.
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if (!calcLiveBlockInfo()) {
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// FIXME: calcLiveBlockInfo found inconsistencies in the live range.
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// I am looking at you, SimpleRegisterCoalescing!
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DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
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const_cast<LiveIntervals&>(LIS)
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.shrinkToUses(const_cast<LiveInterval*>(CurLI));
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UseBlocks.clear();
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ThroughBlocks.clear();
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bool fixed = calcLiveBlockInfo();
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(void)fixed;
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assert(fixed && "Couldn't fix broken live interval");
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}
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DEBUG(dbgs() << "Analyze counted "
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<< UseSlots.size() << " instrs in "
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<< UseBlocks.size() << " blocks, through "
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<< NumThroughBlocks << " blocks.\n");
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}
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/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
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/// where CurLI is live.
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bool SplitAnalysis::calcLiveBlockInfo() {
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ThroughBlocks.resize(MF.getNumBlockIDs());
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NumThroughBlocks = 0;
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if (CurLI->empty())
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return true;
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LiveInterval::const_iterator LVI = CurLI->begin();
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LiveInterval::const_iterator LVE = CurLI->end();
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SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
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UseI = UseSlots.begin();
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UseE = UseSlots.end();
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// Loop over basic blocks where CurLI is live.
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MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
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for (;;) {
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BlockInfo BI;
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BI.MBB = MFI;
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SlotIndex Start, Stop;
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tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
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// LVI is the first live segment overlapping MBB.
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BI.LiveIn = LVI->start <= Start;
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if (!BI.LiveIn)
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BI.Def = LVI->start;
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// Find the first and last uses in the block.
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bool Uses = UseI != UseE && *UseI < Stop;
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if (Uses) {
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BI.FirstUse = *UseI;
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assert(BI.FirstUse >= Start);
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do ++UseI;
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while (UseI != UseE && *UseI < Stop);
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BI.LastUse = UseI[-1];
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assert(BI.LastUse < Stop);
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}
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// Look for gaps in the live range.
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bool hasGap = false;
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BI.LiveOut = true;
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while (LVI->end < Stop) {
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SlotIndex LastStop = LVI->end;
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if (++LVI == LVE || LVI->start >= Stop) {
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BI.Kill = LastStop;
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BI.LiveOut = false;
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break;
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}
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if (LastStop < LVI->start) {
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hasGap = true;
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BI.Kill = LastStop;
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BI.Def = LVI->start;
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}
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}
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// Don't set LiveThrough when the block has a gap.
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BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
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if (Uses)
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UseBlocks.push_back(BI);
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else {
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++NumThroughBlocks;
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ThroughBlocks.set(BI.MBB->getNumber());
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}
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// FIXME: This should never happen. The live range stops or starts without a
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// corresponding use. An earlier pass did something wrong.
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if (!BI.LiveThrough && !Uses)
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return false;
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// LVI is now at LVE or LVI->end >= Stop.
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if (LVI == LVE)
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break;
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// Live segment ends exactly at Stop. Move to the next segment.
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if (LVI->end == Stop && ++LVI == LVE)
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break;
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// Pick the next basic block.
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if (LVI->start < Stop)
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++MFI;
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else
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MFI = LIS.getMBBFromIndex(LVI->start);
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}
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return true;
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}
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bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
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unsigned OrigReg = VRM.getOriginal(CurLI->reg);
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const LiveInterval &Orig = LIS.getInterval(OrigReg);
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assert(!Orig.empty() && "Splitting empty interval?");
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LiveInterval::const_iterator I = Orig.find(Idx);
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// Range containing Idx should begin at Idx.
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if (I != Orig.end() && I->start <= Idx)
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return I->start == Idx;
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// Range does not contain Idx, previous must end at Idx.
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return I != Orig.begin() && (--I)->end == Idx;
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}
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void SplitAnalysis::analyze(const LiveInterval *li) {
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clear();
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CurLI = li;
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analyzeUses();
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}
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//===----------------------------------------------------------------------===//
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// Split Editor
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//===----------------------------------------------------------------------===//
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/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
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SplitEditor::SplitEditor(SplitAnalysis &sa,
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LiveIntervals &lis,
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VirtRegMap &vrm,
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MachineDominatorTree &mdt)
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: SA(sa), LIS(lis), VRM(vrm),
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MRI(vrm.getMachineFunction().getRegInfo()),
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MDT(mdt),
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TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
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TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
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Edit(0),
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OpenIdx(0),
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RegAssign(Allocator)
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{}
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void SplitEditor::reset(LiveRangeEdit &lre) {
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Edit = &lre;
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OpenIdx = 0;
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RegAssign.clear();
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Values.clear();
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// We don't need to clear LiveOutCache, only LiveOutSeen entries are read.
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LiveOutSeen.clear();
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// We don't need an AliasAnalysis since we will only be performing
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// cheap-as-a-copy remats anyway.
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Edit->anyRematerializable(LIS, TII, 0);
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}
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void SplitEditor::dump() const {
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if (RegAssign.empty()) {
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dbgs() << " empty\n";
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return;
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}
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for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
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dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
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dbgs() << '\n';
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}
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VNInfo *SplitEditor::defValue(unsigned RegIdx,
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const VNInfo *ParentVNI,
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SlotIndex Idx) {
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assert(ParentVNI && "Mapping NULL value");
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assert(Idx.isValid() && "Invalid SlotIndex");
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assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
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LiveInterval *LI = Edit->get(RegIdx);
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// Create a new value.
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VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
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// Use insert for lookup, so we can add missing values with a second lookup.
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std::pair<ValueMap::iterator, bool> InsP =
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Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
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// This was the first time (RegIdx, ParentVNI) was mapped.
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// Keep it as a simple def without any liveness.
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if (InsP.second)
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return VNI;
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// If the previous value was a simple mapping, add liveness for it now.
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if (VNInfo *OldVNI = InsP.first->second) {
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SlotIndex Def = OldVNI->def;
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LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
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// No longer a simple mapping.
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InsP.first->second = 0;
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}
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// This is a complex mapping, add liveness for VNI
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SlotIndex Def = VNI->def;
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LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
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return VNI;
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}
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void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
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assert(ParentVNI && "Mapping NULL value");
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VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
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// ParentVNI was either unmapped or already complex mapped. Either way.
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if (!VNI)
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return;
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// This was previously a single mapping. Make sure the old def is represented
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// by a trivial live range.
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SlotIndex Def = VNI->def;
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Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
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VNI = 0;
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}
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// extendRange - Extend the live range to reach Idx.
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// Potentially create phi-def values.
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void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
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assert(Idx.isValid() && "Invalid SlotIndex");
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MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
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assert(IdxMBB && "No MBB at Idx");
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LiveInterval *LI = Edit->get(RegIdx);
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// Is there a def in the same MBB we can extend?
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if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
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return;
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// Now for the fun part. We know that ParentVNI potentially has multiple defs,
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// and we may need to create even more phi-defs to preserve VNInfo SSA form.
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// Perform a search for all predecessor blocks where we know the dominating
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// VNInfo. Insert phi-def VNInfos along the path back to IdxMBB.
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// Initialize the live-out cache the first time it is needed.
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if (LiveOutSeen.empty()) {
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unsigned N = VRM.getMachineFunction().getNumBlockIDs();
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LiveOutSeen.resize(N);
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LiveOutCache.resize(N);
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}
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// Blocks where LI should be live-in.
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SmallVector<MachineDomTreeNode*, 16> LiveIn;
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LiveIn.push_back(MDT[IdxMBB]);
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// Remember if we have seen more than one value.
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bool UniqueVNI = true;
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VNInfo *IdxVNI = 0;
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// Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
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for (unsigned i = 0; i != LiveIn.size(); ++i) {
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MachineBasicBlock *MBB = LiveIn[i]->getBlock();
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assert(!MBB->pred_empty() && "Value live-in to entry block?");
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for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
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PE = MBB->pred_end(); PI != PE; ++PI) {
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MachineBasicBlock *Pred = *PI;
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LiveOutPair &LOP = LiveOutCache[Pred];
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// Is this a known live-out block?
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if (LiveOutSeen.test(Pred->getNumber())) {
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if (VNInfo *VNI = LOP.first) {
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if (IdxVNI && IdxVNI != VNI)
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UniqueVNI = false;
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IdxVNI = VNI;
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}
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continue;
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}
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// First time. LOP is garbage and must be cleared below.
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LiveOutSeen.set(Pred->getNumber());
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// Does Pred provide a live-out value?
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SlotIndex Start, Last;
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tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
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Last = Last.getPrevSlot();
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VNInfo *VNI = LI->extendInBlock(Start, Last);
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LOP.first = VNI;
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if (VNI) {
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LOP.second = MDT[LIS.getMBBFromIndex(VNI->def)];
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if (IdxVNI && IdxVNI != VNI)
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UniqueVNI = false;
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IdxVNI = VNI;
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continue;
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}
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LOP.second = 0;
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// No, we need a live-in value for Pred as well
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if (Pred != IdxMBB)
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LiveIn.push_back(MDT[Pred]);
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else
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UniqueVNI = false; // Loopback to IdxMBB, ask updateSSA() for help.
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}
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}
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// We may need to add phi-def values to preserve the SSA form.
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if (UniqueVNI) {
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LiveOutPair LOP(IdxVNI, MDT[LIS.getMBBFromIndex(IdxVNI->def)]);
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// Update LiveOutCache, but skip IdxMBB at LiveIn[0].
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for (unsigned i = 1, e = LiveIn.size(); i != e; ++i)
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LiveOutCache[LiveIn[i]->getBlock()] = LOP;
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} else
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IdxVNI = updateSSA(RegIdx, LiveIn, Idx, IdxMBB);
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// Since we went through the trouble of a full BFS visiting all reaching defs,
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// the values in LiveIn are now accurate. No more phi-defs are needed
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// for these blocks, so we can color the live ranges.
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for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
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MachineBasicBlock *MBB = LiveIn[i]->getBlock();
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SlotIndex Start = LIS.getMBBStartIdx(MBB);
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VNInfo *VNI = LiveOutCache[MBB].first;
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// Anything in LiveIn other than IdxMBB is live-through.
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// In IdxMBB, we should stop at Idx unless the same value is live-out.
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if (MBB == IdxMBB && IdxVNI != VNI)
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LI->addRange(LiveRange(Start, Idx.getNextSlot(), IdxVNI));
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else
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LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
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}
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}
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VNInfo *SplitEditor::updateSSA(unsigned RegIdx,
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SmallVectorImpl<MachineDomTreeNode*> &LiveIn,
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SlotIndex Idx,
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const MachineBasicBlock *IdxMBB) {
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// This is essentially the same iterative algorithm that SSAUpdater uses,
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// except we already have a dominator tree, so we don't have to recompute it.
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LiveInterval *LI = Edit->get(RegIdx);
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VNInfo *IdxVNI = 0;
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unsigned Changes;
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do {
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Changes = 0;
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// Propagate live-out values down the dominator tree, inserting phi-defs
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// when necessary. Since LiveIn was created by a BFS, going backwards makes
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// it more likely for us to visit immediate dominators before their
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// children.
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for (unsigned i = LiveIn.size(); i; --i) {
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MachineDomTreeNode *Node = LiveIn[i-1];
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MachineBasicBlock *MBB = Node->getBlock();
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MachineDomTreeNode *IDom = Node->getIDom();
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LiveOutPair IDomValue;
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// We need a live-in value to a block with no immediate dominator?
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// This is probably an unreachable block that has survived somehow.
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bool needPHI = !IDom || !LiveOutSeen.test(IDom->getBlock()->getNumber());
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// IDom dominates all of our predecessors, but it may not be the immediate
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// dominator. Check if any of them have live-out values that are properly
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// dominated by IDom. If so, we need a phi-def here.
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if (!needPHI) {
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|
IDomValue = LiveOutCache[IDom->getBlock()];
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
LiveOutPair Value = LiveOutCache[*PI];
|
|
if (!Value.first || Value.first == IDomValue.first)
|
|
continue;
|
|
// This predecessor is carrying something other than IDomValue.
|
|
// It could be because IDomValue hasn't propagated yet, or it could be
|
|
// because MBB is in the dominance frontier of that value.
|
|
if (MDT.dominates(IDom, Value.second)) {
|
|
needPHI = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Create a phi-def if required.
|
|
if (needPHI) {
|
|
++Changes;
|
|
SlotIndex Start = LIS.getMBBStartIdx(MBB);
|
|
VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
|
|
VNI->setIsPHIDef(true);
|
|
// We no longer need LI to be live-in.
|
|
LiveIn.erase(LiveIn.begin()+(i-1));
|
|
// Blocks in LiveIn are either IdxMBB, or have a value live-through.
|
|
if (MBB == IdxMBB)
|
|
IdxVNI = VNI;
|
|
// Check if we need to update live-out info.
|
|
LiveOutPair &LOP = LiveOutCache[MBB];
|
|
if (LOP.second == Node || !LiveOutSeen.test(MBB->getNumber())) {
|
|
// We already have a live-out defined in MBB, so this must be IdxMBB.
|
|
assert(MBB == IdxMBB && "Adding phi-def to known live-out");
|
|
LI->addRange(LiveRange(Start, Idx.getNextSlot(), VNI));
|
|
} else {
|
|
// This phi-def is also live-out, so color the whole block.
|
|
LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
|
|
LOP = LiveOutPair(VNI, Node);
|
|
}
|
|
} else if (IDomValue.first) {
|
|
// No phi-def here. Remember incoming value for IdxMBB.
|
|
if (MBB == IdxMBB) {
|
|
IdxVNI = IDomValue.first;
|
|
// IdxMBB need not be live-out.
|
|
if (!LiveOutSeen.test(MBB->getNumber()))
|
|
continue;
|
|
}
|
|
assert(LiveOutSeen.test(MBB->getNumber()) && "Expected live-out block");
|
|
// Propagate IDomValue if needed:
|
|
// MBB is live-out and doesn't define its own value.
|
|
LiveOutPair &LOP = LiveOutCache[MBB];
|
|
if (LOP.second != Node && LOP.first != IDomValue.first) {
|
|
++Changes;
|
|
LOP = IDomValue;
|
|
}
|
|
}
|
|
}
|
|
} while (Changes);
|
|
|
|
assert(IdxVNI && "Didn't find value for Idx");
|
|
return IdxVNI;
|
|
}
|
|
|
|
VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
|
|
VNInfo *ParentVNI,
|
|
SlotIndex UseIdx,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) {
|
|
MachineInstr *CopyMI = 0;
|
|
SlotIndex Def;
|
|
LiveInterval *LI = Edit->get(RegIdx);
|
|
|
|
// Attempt cheap-as-a-copy rematerialization.
|
|
LiveRangeEdit::Remat RM(ParentVNI);
|
|
if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
|
|
Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
|
|
} else {
|
|
// Can't remat, just insert a copy from parent.
|
|
CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
|
|
.addReg(Edit->getReg());
|
|
Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
|
|
}
|
|
|
|
// Define the value in Reg.
|
|
VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
|
|
VNI->setCopy(CopyMI);
|
|
return VNI;
|
|
}
|
|
|
|
/// Create a new virtual register and live interval.
|
|
unsigned SplitEditor::openIntv() {
|
|
assert(!OpenIdx && "Previous LI not closed before openIntv");
|
|
|
|
// Create the complement as index 0.
|
|
if (Edit->empty())
|
|
Edit->create(LIS, VRM);
|
|
|
|
// Create the open interval.
|
|
OpenIdx = Edit->size();
|
|
Edit->create(LIS, VRM);
|
|
return OpenIdx;
|
|
}
|
|
|
|
void SplitEditor::selectIntv(unsigned Idx) {
|
|
assert(Idx != 0 && "Cannot select the complement interval");
|
|
assert(Idx < Edit->size() && "Can only select previously opened interval");
|
|
OpenIdx = Idx;
|
|
}
|
|
|
|
SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before enterIntvBefore");
|
|
DEBUG(dbgs() << " enterIntvBefore " << Idx);
|
|
Idx = Idx.getBaseIndex();
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx;
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "enterIntvBefore called with invalid index");
|
|
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
|
|
assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
|
|
SlotIndex End = LIS.getMBBEndIdx(&MBB);
|
|
SlotIndex Last = End.getPrevSlot();
|
|
DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return End;
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id);
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
|
|
LIS.getLastSplitPoint(Edit->getParent(), &MBB));
|
|
RegAssign.insert(VNI->def, End, OpenIdx);
|
|
DEBUG(dump());
|
|
return VNI->def;
|
|
}
|
|
|
|
/// useIntv - indicate that all instructions in MBB should use OpenLI.
|
|
void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
|
|
useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
|
|
}
|
|
|
|
void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
|
|
assert(OpenIdx && "openIntv not called before useIntv");
|
|
DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
|
|
RegAssign.insert(Start, End, OpenIdx);
|
|
DEBUG(dump());
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvAfter");
|
|
DEBUG(dbgs() << " leaveIntvAfter " << Idx);
|
|
|
|
// The interval must be live beyond the instruction at Idx.
|
|
Idx = Idx.getBoundaryIndex();
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx.getNextSlot();
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "No instruction at index");
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
|
|
llvm::next(MachineBasicBlock::iterator(MI)));
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvBefore");
|
|
DEBUG(dbgs() << " leaveIntvBefore " << Idx);
|
|
|
|
// The interval must be live into the instruction at Idx.
|
|
Idx = Idx.getBoundaryIndex();
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx.getNextSlot();
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "No instruction at index");
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
|
|
SlotIndex Start = LIS.getMBBStartIdx(&MBB);
|
|
DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
|
|
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Start;
|
|
}
|
|
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
|
|
MBB.SkipPHIsAndLabels(MBB.begin()));
|
|
RegAssign.insert(Start, VNI->def, OpenIdx);
|
|
DEBUG(dump());
|
|
return VNI->def;
|
|
}
|
|
|
|
void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
|
|
assert(OpenIdx && "openIntv not called before overlapIntv");
|
|
const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
|
|
assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
|
|
"Parent changes value in extended range");
|
|
assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
|
|
"Range cannot span basic blocks");
|
|
|
|
// The complement interval will be extended as needed by extendRange().
|
|
if (ParentVNI)
|
|
markComplexMapped(0, ParentVNI);
|
|
DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
|
|
RegAssign.insert(Start, End, OpenIdx);
|
|
DEBUG(dump());
|
|
}
|
|
|
|
/// closeIntv - Indicate that we are done editing the currently open
|
|
/// LiveInterval, and ranges can be trimmed.
|
|
void SplitEditor::closeIntv() {
|
|
assert(OpenIdx && "openIntv not called before closeIntv");
|
|
OpenIdx = 0;
|
|
}
|
|
|
|
/// transferSimpleValues - Transfer all simply defined values to the new live
|
|
/// ranges.
|
|
/// Values that were rematerialized or that have multiple defs are left alone.
|
|
bool SplitEditor::transferSimpleValues() {
|
|
bool Skipped = false;
|
|
RegAssignMap::const_iterator AssignI = RegAssign.begin();
|
|
for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
|
|
ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
|
|
DEBUG(dbgs() << " blit " << *ParentI << ':');
|
|
VNInfo *ParentVNI = ParentI->valno;
|
|
// RegAssign has holes where RegIdx 0 should be used.
|
|
SlotIndex Start = ParentI->start;
|
|
AssignI.advanceTo(Start);
|
|
do {
|
|
unsigned RegIdx;
|
|
SlotIndex End = ParentI->end;
|
|
if (!AssignI.valid()) {
|
|
RegIdx = 0;
|
|
} else if (AssignI.start() <= Start) {
|
|
RegIdx = AssignI.value();
|
|
if (AssignI.stop() < End) {
|
|
End = AssignI.stop();
|
|
++AssignI;
|
|
}
|
|
} else {
|
|
RegIdx = 0;
|
|
End = std::min(End, AssignI.start());
|
|
}
|
|
DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
|
|
if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
|
|
DEBUG(dbgs() << ':' << VNI->id);
|
|
Edit->get(RegIdx)->addRange(LiveRange(Start, End, VNI));
|
|
} else
|
|
Skipped = true;
|
|
Start = End;
|
|
} while (Start != ParentI->end);
|
|
DEBUG(dbgs() << '\n');
|
|
}
|
|
return Skipped;
|
|
}
|
|
|
|
void SplitEditor::extendPHIKillRanges() {
|
|
// Extend live ranges to be live-out for successor PHI values.
|
|
for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
|
|
E = Edit->getParent().vni_end(); I != E; ++I) {
|
|
const VNInfo *PHIVNI = *I;
|
|
if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
|
|
continue;
|
|
unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
|
|
MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
|
|
// The predecessor may not have a live-out value. That is OK, like an
|
|
// undef PHI operand.
|
|
if (Edit->getParent().liveAt(End)) {
|
|
assert(RegAssign.lookup(End) == RegIdx &&
|
|
"Different register assignment in phi predecessor");
|
|
extendRange(RegIdx, End);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// rewriteAssigned - Rewrite all uses of Edit->getReg().
|
|
void SplitEditor::rewriteAssigned(bool ExtendRanges) {
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
|
|
RE = MRI.reg_end(); RI != RE;) {
|
|
MachineOperand &MO = RI.getOperand();
|
|
MachineInstr *MI = MO.getParent();
|
|
++RI;
|
|
// LiveDebugVariables should have handled all DBG_VALUE instructions.
|
|
if (MI->isDebugValue()) {
|
|
DEBUG(dbgs() << "Zapping " << *MI);
|
|
MO.setReg(0);
|
|
continue;
|
|
}
|
|
|
|
// <undef> operands don't really read the register, so just assign them to
|
|
// the complement.
|
|
if (MO.isUse() && MO.isUndef()) {
|
|
MO.setReg(Edit->get(0)->reg);
|
|
continue;
|
|
}
|
|
|
|
SlotIndex Idx = LIS.getInstructionIndex(MI);
|
|
if (MO.isDef())
|
|
Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
|
|
|
|
// Rewrite to the mapped register at Idx.
|
|
unsigned RegIdx = RegAssign.lookup(Idx);
|
|
MO.setReg(Edit->get(RegIdx)->reg);
|
|
DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
|
|
<< Idx << ':' << RegIdx << '\t' << *MI);
|
|
|
|
// Extend liveness to Idx if the instruction reads reg.
|
|
if (!ExtendRanges)
|
|
continue;
|
|
|
|
// Skip instructions that don't read Reg.
|
|
if (MO.isDef()) {
|
|
if (!MO.getSubReg() && !MO.isEarlyClobber())
|
|
continue;
|
|
// We may wan't to extend a live range for a partial redef, or for a use
|
|
// tied to an early clobber.
|
|
Idx = Idx.getPrevSlot();
|
|
if (!Edit->getParent().liveAt(Idx))
|
|
continue;
|
|
} else
|
|
Idx = Idx.getUseIndex();
|
|
|
|
extendRange(RegIdx, Idx);
|
|
}
|
|
}
|
|
|
|
void SplitEditor::deleteRematVictims() {
|
|
SmallVector<MachineInstr*, 8> Dead;
|
|
for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
|
|
LiveInterval *LI = *I;
|
|
for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
|
|
LII != LIE; ++LII) {
|
|
// Dead defs end at the store slot.
|
|
if (LII->end != LII->valno->def.getNextSlot())
|
|
continue;
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
|
|
assert(MI && "Missing instruction for dead def");
|
|
MI->addRegisterDead(LI->reg, &TRI);
|
|
|
|
if (!MI->allDefsAreDead())
|
|
continue;
|
|
|
|
DEBUG(dbgs() << "All defs dead: " << *MI);
|
|
Dead.push_back(MI);
|
|
}
|
|
}
|
|
|
|
if (Dead.empty())
|
|
return;
|
|
|
|
Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
|
|
}
|
|
|
|
void SplitEditor::finish() {
|
|
assert(OpenIdx == 0 && "Previous LI not closed before rewrite");
|
|
++NumFinished;
|
|
|
|
// At this point, the live intervals in Edit contain VNInfos corresponding to
|
|
// the inserted copies.
|
|
|
|
// Add the original defs from the parent interval.
|
|
for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
|
|
E = Edit->getParent().vni_end(); I != E; ++I) {
|
|
const VNInfo *ParentVNI = *I;
|
|
if (ParentVNI->isUnused())
|
|
continue;
|
|
unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
|
|
VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
|
|
VNI->setIsPHIDef(ParentVNI->isPHIDef());
|
|
VNI->setCopy(ParentVNI->getCopy());
|
|
|
|
// Mark rematted values as complex everywhere to force liveness computation.
|
|
// The new live ranges may be truncated.
|
|
if (Edit->didRematerialize(ParentVNI))
|
|
for (unsigned i = 0, e = Edit->size(); i != e; ++i)
|
|
markComplexMapped(i, ParentVNI);
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
// Every new interval must have a def by now, otherwise the split is bogus.
|
|
for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
|
|
assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
|
|
#endif
|
|
|
|
// Transfer the simply mapped values, check if any are complex.
|
|
bool Complex = transferSimpleValues();
|
|
if (Complex)
|
|
extendPHIKillRanges();
|
|
else
|
|
++NumSimple;
|
|
|
|
// Rewrite virtual registers, possibly extending ranges.
|
|
rewriteAssigned(Complex);
|
|
|
|
// Delete defs that were rematted everywhere.
|
|
if (Complex)
|
|
deleteRematVictims();
|
|
|
|
// Get rid of unused values and set phi-kill flags.
|
|
for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
|
|
(*I)->RenumberValues(LIS);
|
|
|
|
// Now check if any registers were separated into multiple components.
|
|
ConnectedVNInfoEqClasses ConEQ(LIS);
|
|
for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
|
|
// Don't use iterators, they are invalidated by create() below.
|
|
LiveInterval *li = Edit->get(i);
|
|
unsigned NumComp = ConEQ.Classify(li);
|
|
if (NumComp <= 1)
|
|
continue;
|
|
DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
|
|
SmallVector<LiveInterval*, 8> dups;
|
|
dups.push_back(li);
|
|
for (unsigned i = 1; i != NumComp; ++i)
|
|
dups.push_back(&Edit->create(LIS, VRM));
|
|
ConEQ.Distribute(&dups[0], MRI);
|
|
}
|
|
|
|
// Calculate spill weight and allocation hints for new intervals.
|
|
Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Single Block Splitting
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
|
|
/// may be an advantage to split CurLI for the duration of the block.
|
|
bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
|
|
// If CurLI is local to one block, there is no point to splitting it.
|
|
if (UseBlocks.size() <= 1)
|
|
return false;
|
|
// Add blocks with multiple uses.
|
|
for (unsigned i = 0, e = UseBlocks.size(); i != e; ++i) {
|
|
const BlockInfo &BI = UseBlocks[i];
|
|
if (BI.FirstUse == BI.LastUse)
|
|
continue;
|
|
Blocks.insert(BI.MBB);
|
|
}
|
|
return !Blocks.empty();
|
|
}
|
|
|
|
void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
|
|
openIntv();
|
|
SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
|
|
SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstUse,
|
|
LastSplitPoint));
|
|
if (!BI.LiveOut || BI.LastUse < LastSplitPoint) {
|
|
useIntv(SegStart, leaveIntvAfter(BI.LastUse));
|
|
} else {
|
|
// The last use is after the last valid split point.
|
|
SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
|
|
useIntv(SegStart, SegStop);
|
|
overlapIntv(SegStop, BI.LastUse);
|
|
}
|
|
closeIntv();
|
|
}
|
|
|
|
/// splitSingleBlocks - Split CurLI into a separate live interval inside each
|
|
/// basic block in Blocks.
|
|
void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
|
|
DEBUG(dbgs() << " splitSingleBlocks for " << Blocks.size() << " blocks.\n");
|
|
ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA.getUseBlocks();
|
|
for (unsigned i = 0; i != UseBlocks.size(); ++i) {
|
|
const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
|
|
if (Blocks.count(BI.MBB))
|
|
splitSingleBlock(BI);
|
|
}
|
|
finish();
|
|
}
|