Chad Rosier 16455ce1a4 When in ARM mode, LDRH/STRH require special handling of negative offsets. ... For correctness, disable this for now. rdar://10418009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8		2011-11-10 21:09:49 +00:00
..
ARM	When in ARM mode, LDRH/STRH require special handling of negative offsets.	2011-11-10 21:09:49 +00:00
CBackend
CellSPU	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
CPP
Generic
MBlaze	Change the default scheduler from Latency to ILP, since Latency	2011-10-24 17:45:02 +00:00
Mips	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
MSP430	Remove the explicit request for "Latency" scheduling from MSP430,	2011-10-24 17:53:16 +00:00
PowerPC	test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now.	2011-10-28 23:11:03 +00:00
PTX	fixed global array handling for ptx to use the correct bit widths	2011-11-03 19:24:46 +00:00
SPARC
Thumb	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
Thumb2
X86	test/CodeGen/X86/lsr-loop-exit-cond.ll: Try to appease linux and freebsd bots to specify explicit -mtriple=x86_64-darwin.	2011-11-10 14:18:59 +00:00
XCore	Don't fold negative offsets into cp / dp accesses to avoid relocation errors.	2011-11-01 11:31:53 +00:00