llvm-6502/test/CodeGen/SystemZ/risbg-03.ll
Ulrich Weigand cb1b3ad4e1 [SystemZ] Support RISBGN instruction on zEC12
So far, we do not yet support any instruction specific to zEC12.
Most of the facilities added with zEC12 are indeed not very useful
to compiler code generation, but there is one exception: the
miscellaneous-extensions facility provides the RISBGN instruction,
which is a variant of RISBG that does not set the condition code.

Add support for this facility, MC support for RISBGN, and CodeGen
support for prefering RISBGN over RISBG on zEC12, unless we can
actually make use of the condition code set by RISBG.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233690 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 12:58:17 +00:00

31 lines
740 B
LLVM

; Test use of RISBG vs RISBGN on zEC12.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
; On zEC12, we generally prefer RISBGN.
define i64 @f1(i64 %a, i64 %b) {
; CHECK-LABEL: f1:
; CHECK: risbgn %r2, %r3, 60, 62, 0
; CHECK: br %r14
%anda = and i64 %a, -15
%andb = and i64 %b, 14
%or = or i64 %anda, %andb
ret i64 %or
}
; But we may fall back to RISBG if we can use the condition code.
define i64 @f2(i64 %a, i64 %b, i32* %c) {
; CHECK-LABEL: f2:
; CHECK: risbg %r2, %r3, 60, 62, 0
; CHECK-NEXT: ipm
; CHECK: br %r14
%anda = and i64 %a, -15
%andb = and i64 %b, 14
%or = or i64 %anda, %andb
%cmp = icmp sgt i64 %or, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* %c, align 4
ret i64 %or
}