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28ee4fdf20
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16 jalr instruction. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157730 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
1.4 KiB
TableGen
35 lines
1.4 KiB
TableGen
//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips16 instructions.
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//
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//===----------------------------------------------------------------------===//
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let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
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isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0 in
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def RET16 : FRR16_JALRC < (outs), (ins CPURAReg:$target),
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"jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>;
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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"!ADJCALLSTACKUP $amt1",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in
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def JumpLinkReg16:
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FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops),
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"jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
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