mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f0144127b9
it is highly specific to the object file that will be generated in the end, this introduces a new TargetLoweringObjectFile interface that is implemented for each of ELF/MachO/COFF/Alpha/PIC16 and XCore. Though still is still a brutal and ugly refactoring, this is a major step towards goodness. This patch also: 1. fixes a bunch of dangling pointer problems in the PIC16 backend. 2. disables the TargetLowering copy ctor which PIC16 was accidentally using. 3. gets us closer to xcore having its own crazy target section flags and pic16 not having to shadow sections with its own objects. 4. fixes wierdness where ELF targets would set CStringSection but not CStringSection_. Factor the code better. 5. fixes some bugs in string lowering on ELF targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
255 lines
9.8 KiB
C++
255 lines
9.8 KiB
C++
//===-- ARMTargetAsmInfo.cpp - ARM asm properties ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declarations of the ARMTargetAsmInfo properties.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMTargetAsmInfo.h"
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#include "ARMTargetMachine.h"
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#include <cstring>
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#include <cctype>
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using namespace llvm;
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const char *const llvm::arm_asm_table[] = {
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"{r0}", "r0",
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"{r1}", "r1",
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"{r2}", "r2",
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"{r3}", "r3",
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"{r4}", "r4",
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"{r5}", "r5",
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"{r6}", "r6",
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"{r7}", "r7",
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"{r8}", "r8",
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"{r9}", "r9",
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"{r10}", "r10",
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"{r11}", "r11",
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"{r12}", "r12",
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"{r13}", "r13",
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"{r14}", "r14",
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"{lr}", "lr",
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"{sp}", "sp",
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"{ip}", "ip",
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"{fp}", "fp",
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"{sl}", "sl",
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"{memory}", "memory",
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"{cc}", "cc",
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0,0
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};
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ARMDarwinTargetAsmInfo::ARMDarwinTargetAsmInfo(const ARMBaseTargetMachine &TM):
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ARMTargetAsmInfo<DarwinTargetAsmInfo>(TM) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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ZeroDirective = "\t.space\t";
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ZeroFillDirective = "\t.zerofill\t"; // Uses .zerofill
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SetDirective = "\t.set\t";
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ProtectedDirective = NULL;
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HasDotTypeDotSizeDirective = false;
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SupportsDebugInformation = true;
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}
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ARMELFTargetAsmInfo::ARMELFTargetAsmInfo(const ARMBaseTargetMachine &TM):
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ARMTargetAsmInfo<ELFTargetAsmInfo>(TM) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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NeedsSet = false;
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HasLEB128 = true;
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AbsoluteDebugSectionOffsets = true;
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CStringSection = ".rodata.str";
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PrivateGlobalPrefix = ".L";
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WeakRefDirective = "\t.weak\t";
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SetDirective = "\t.set\t";
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DwarfRequiresFrameSection = false;
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DwarfAbbrevSection = "\t.section\t.debug_abbrev,\"\",%progbits";
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DwarfInfoSection = "\t.section\t.debug_info,\"\",%progbits";
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DwarfLineSection = "\t.section\t.debug_line,\"\",%progbits";
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DwarfFrameSection = "\t.section\t.debug_frame,\"\",%progbits";
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DwarfPubNamesSection ="\t.section\t.debug_pubnames,\"\",%progbits";
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DwarfPubTypesSection ="\t.section\t.debug_pubtypes,\"\",%progbits";
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DwarfStrSection = "\t.section\t.debug_str,\"\",%progbits";
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DwarfLocSection = "\t.section\t.debug_loc,\"\",%progbits";
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DwarfARangesSection = "\t.section\t.debug_aranges,\"\",%progbits";
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DwarfRangesSection = "\t.section\t.debug_ranges,\"\",%progbits";
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DwarfMacroInfoSection = "\t.section\t.debug_macinfo,\"\",%progbits";
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if (Subtarget->isAAPCS_ABI()) {
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StaticCtorsSection = "\t.section .init_array,\"aw\",%init_array";
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StaticDtorsSection = "\t.section .fini_array,\"aw\",%fini_array";
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} else {
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StaticCtorsSection = "\t.section .ctors,\"aw\",%progbits";
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StaticDtorsSection = "\t.section .dtors,\"aw\",%progbits";
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}
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SupportsDebugInformation = true;
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}
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/// Count the number of comma-separated arguments.
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/// Do not try to detect errors.
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template <class BaseTAI>
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unsigned ARMTargetAsmInfo<BaseTAI>::countArguments(const char* p) const {
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unsigned count = 0;
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while (*p && isspace(*p) && *p != '\n')
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p++;
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count++;
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while (*p && *p!='\n' &&
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strncmp(p, BaseTAI::CommentString,
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strlen(BaseTAI::CommentString))!=0) {
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if (*p==',')
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count++;
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p++;
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}
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return count;
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}
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/// Count the length of a string enclosed in quote characters.
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/// Do not try to detect errors.
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template <class BaseTAI>
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unsigned ARMTargetAsmInfo<BaseTAI>::countString(const char* p) const {
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unsigned count = 0;
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while (*p && isspace(*p) && *p!='\n')
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p++;
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if (!*p || *p != '\"')
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return count;
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while (*++p && *p != '\"')
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count++;
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return count;
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}
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/// ARM-specific version of TargetAsmInfo::getInlineAsmLength.
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template <class BaseTAI>
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unsigned ARMTargetAsmInfo<BaseTAI>::getInlineAsmLength(const char *s) const {
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// Make a lowercase-folded version of s for counting purposes.
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char *q, *s_copy = (char *)malloc(strlen(s) + 1);
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strcpy(s_copy, s);
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for (q=s_copy; *q; q++)
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*q = tolower(*q);
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const char *Str = s_copy;
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// Count the number of bytes in the asm.
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bool atInsnStart = true;
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bool inTextSection = true;
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unsigned Length = 0;
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for (; *Str; ++Str) {
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if (atInsnStart) {
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// Skip whitespace
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while (*Str && isspace(*Str) && *Str != '\n')
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Str++;
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// Skip label
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for (const char* p = Str; *p && !isspace(*p); p++)
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if (*p == ':') {
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Str = p+1;
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while (*Str && isspace(*Str) && *Str != '\n')
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Str++;
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break;
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}
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if (*Str == 0) break;
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// Ignore everything from comment char(s) to EOL
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if (strncmp(Str, BaseTAI::CommentString,
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strlen(BaseTAI::CommentString)) == 0)
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atInsnStart = false;
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// FIXME do something like the following for non-Darwin
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else if (*Str == '.' && Subtarget->isTargetDarwin()) {
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// Directive.
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atInsnStart = false;
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// Some change the section, but don't generate code.
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if (strncmp(Str, ".literal4", strlen(".literal4"))==0 ||
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strncmp(Str, ".literal8", strlen(".literal8"))==0 ||
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strncmp(Str, ".const", strlen(".const"))==0 ||
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strncmp(Str, ".constructor", strlen(".constructor"))==0 ||
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strncmp(Str, ".cstring", strlen(".cstring"))==0 ||
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strncmp(Str, ".data", strlen(".data"))==0 ||
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strncmp(Str, ".destructor", strlen(".destructor"))==0 ||
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strncmp(Str, ".fvmlib_init0", strlen(".fvmlib_init0"))==0 ||
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strncmp(Str, ".fvmlib_init1", strlen(".fvmlib_init1"))==0 ||
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strncmp(Str, ".mod_init_func", strlen(".mod_init_func"))==0 ||
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strncmp(Str, ".mod_term_func", strlen(".mod_term_func"))==0 ||
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strncmp(Str, ".picsymbol_stub", strlen(".picsymbol_stub"))==0 ||
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strncmp(Str, ".symbol_stub", strlen(".symbol_stub"))==0 ||
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strncmp(Str, ".static_data", strlen(".static_data"))==0 ||
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strncmp(Str, ".section", strlen(".section"))==0 ||
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strncmp(Str, ".lazy_symbol_pointer", strlen(".lazy_symbol_pointer"))==0 ||
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strncmp(Str, ".non_lazy_symbol_pointer", strlen(".non_lazy_symbol_pointer"))==0 ||
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strncmp(Str, ".dyld", strlen(".dyld"))==0 ||
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strncmp(Str, ".const_data", strlen(".const_data"))==0 ||
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strncmp(Str, ".objc", strlen(".objc"))==0 || //// many directives
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strncmp(Str, ".static_const", strlen(".static_const"))==0)
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inTextSection=false;
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else if (strncmp(Str, ".text", strlen(".text"))==0)
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inTextSection = true;
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// Some can't really be handled without implementing significant pieces
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// of an assembler. Others require dynamic adjustment of block sizes in
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// AdjustBBOffsetsAfter; it's a big compile-time speed hit to check every
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// instruction in there, and none of these are currently used in the kernel.
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else if (strncmp(Str, ".macro", strlen(".macro"))==0 ||
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strncmp(Str, ".if", strlen(".if"))==0 ||
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strncmp(Str, ".align", strlen(".align"))==0 ||
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strncmp(Str, ".fill", strlen(".fill"))==0 ||
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strncmp(Str, ".space", strlen(".space"))==0 ||
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strncmp(Str, ".zerofill", strlen(".zerofill"))==0 ||
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strncmp(Str, ".p2align", strlen(".p2align"))==0 ||
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strncmp(Str, ".p2alignw", strlen(".p2alignw"))==0 ||
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strncmp(Str, ".p2alignl", strlen(".p2alignl"))==0 ||
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strncmp(Str, ".align32", strlen(".p2align32"))==0 ||
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strncmp(Str, ".include", strlen(".include"))==0)
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cerr << "Directive " << Str << " in asm may lead to invalid offsets for" <<
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" constant pools (the assembler will tell you if this happens).\n";
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// Some generate code, but this is only interesting in the text section.
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else if (inTextSection) {
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if (strncmp(Str, ".long", strlen(".long"))==0)
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Length += 4*countArguments(Str+strlen(".long"));
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else if (strncmp(Str, ".short", strlen(".short"))==0)
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Length += 2*countArguments(Str+strlen(".short"));
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else if (strncmp(Str, ".byte", strlen(".byte"))==0)
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Length += 1*countArguments(Str+strlen(".byte"));
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else if (strncmp(Str, ".single", strlen(".single"))==0)
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Length += 4*countArguments(Str+strlen(".single"));
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else if (strncmp(Str, ".double", strlen(".double"))==0)
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Length += 8*countArguments(Str+strlen(".double"));
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else if (strncmp(Str, ".quad", strlen(".quad"))==0)
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Length += 16*countArguments(Str+strlen(".quad"));
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else if (strncmp(Str, ".ascii", strlen(".ascii"))==0)
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Length += countString(Str+strlen(".ascii"));
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else if (strncmp(Str, ".asciz", strlen(".asciz"))==0)
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Length += countString(Str+strlen(".asciz"))+1;
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}
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} else if (inTextSection) {
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// An instruction
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atInsnStart = false;
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if (Subtarget->isThumb()) { // FIXME thumb2
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// BL and BLX <non-reg> are 4 bytes, all others 2.
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if (strncmp(Str, "blx", strlen("blx"))==0) {
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const char* p = Str+3;
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while (*p && isspace(*p))
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p++;
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if (*p == 'r' || *p=='R')
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Length += 2; // BLX reg
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else
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Length += 4; // BLX non-reg
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} else if (strncmp(Str, "bl", strlen("bl"))==0)
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Length += 4; // BL
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else
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Length += 2; // Thumb anything else
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}
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else
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Length += 4; // ARM
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}
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}
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if (*Str == '\n' || *Str == BaseTAI::SeparatorChar)
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atInsnStart = true;
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}
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free(s_copy);
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return Length;
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}
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// Instantiate default implementation.
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TEMPLATE_INSTANTIATION(class ARMTargetAsmInfo<TargetAsmInfo>);
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