Matt Arsenault 16fc5e9c0f R600/SI: Remove v_sub_f64 pseudo ... The expansion code does the same thing. Since the operands were not defined with the correct types, this has the side effect of fixing operand folding since the expanded pseudo would never use SGPRs or inline immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230072 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-20 22:10:45 +00:00
..
AArch64	AArch64: Safely handle the incoming sret call argument.	2015-02-16 18:10:47 +00:00
ARM	[ARM] Re-re-apply VLD1/VST1 base-update combine.	2015-02-19 23:52:41 +00:00
BPF	bpf: add missing lit.local.cfg	2015-01-24 18:20:52 +00:00
CPP
Generic	overloaded-intrinsic-name: exercise anyptr on struct	2015-01-27 20:03:08 +00:00
Hexagon	[Hexagon] Factoring classes out of store patterns.	2015-02-09 20:33:46 +00:00
Inputs	IR: Move MDLocation into place	2015-01-14 22:27:36 +00:00
Mips	Reversed revision 229706. The reason is regression, which is caused by the	2015-02-20 20:26:52 +00:00
MSP430
NVPTX	[NVPTX] Emit .pragma "nounroll" for loops marked with nounroll	2015-02-01 02:27:45 +00:00
PowerPC	I incorrectly marked the VORC instruction as isCommutable when I added it.	2015-02-20 15:54:58 +00:00
R600	R600/SI: Remove v_sub_f64 pseudo	2015-02-20 22:10:45 +00:00
SPARC	SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too	2015-02-16 21:47:58 +00:00
SystemZ	[SystemZ] Support all TLS access models - CodeGen part	2015-02-18 09:13:27 +00:00
Thumb	IR: Move MDLocation into place	2015-01-14 22:27:36 +00:00
Thumb2	Make buildbots better.	2015-02-11 12:24:09 +00:00
X86	[X86][FastIsel] Teach how to select float-half conversion intrinsics.	2015-02-20 19:37:14 +00:00
XCore	Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation	2015-02-20 02:15:36 +00:00