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we need to handle %ccr reg in a special way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@990 91177308-0d34-0410-b5e6-96231b3b80d8
1191 lines
36 KiB
C++
1191 lines
36 KiB
C++
#include "llvm/CodeGen/PhyRegAlloc.h"
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//***TODO: There are several places we add instructions. Validate the order
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// of adding these instructions.
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cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
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"enable register allocation debugging information",
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clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
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clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
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clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
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//----------------------------------------------------------------------------
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// Constructor: Init local composite objects and create register classes.
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//----------------------------------------------------------------------------
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PhyRegAlloc::PhyRegAlloc(const Method *const M,
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const TargetMachine& tm,
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MethodLiveVarInfo *const Lvi)
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: RegClassList(),
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Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
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MRI( tm.getRegInfo() ),
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NumOfRegClasses(MRI.getNumOfRegClasses()),
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AddedInstrMap(), StackOffsets()
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{
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// **TODO: use an actual reserved color list
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ReservedColorListType *RCL = new ReservedColorListType();
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// create each RegisterClass and put in RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
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RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
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// **TODO: Init to the correct value. Also reset this to the correct
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// value at the start of each instruction. Need a way to track max used
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int curOffset4TmpSpills =0 ;
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}
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::createIGNodeListsAndIGs()
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{
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if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
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// hash map iterator
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LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
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// hash map end
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LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
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for( ; HMI != HMIEnd ; ++HMI ) {
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if( (*HMI).first ) {
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LiveRange *L = (*HMI).second; // get the LiveRange
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if( !L) {
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if( DEBUG_RA) {
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cout << "\n*?!?Warning: Null liver range found for: ";
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printValue( (*HMI).first) ; cout << endl;
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}
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continue;
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}
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// if the Value * is not null, and LR
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// is not yet written to the IGNodeList
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if( !(L->getUserIGNode()) ) {
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RegClass *const RC = // RegClass of first value in the LR
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//RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
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RegClassList[ L->getRegClass()->getID() ];
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RC-> addLRToIG( L ); // add this LR to an IG
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}
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}
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}
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// init RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->createInterferenceGraph();
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if( DEBUG_RA)
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cout << "LRLists Created!" << endl;
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}
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//----------------------------------------------------------------------------
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// This method will add all interferences at for a given instruction.
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// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
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// class as that of live var. The live var passed to this function is the
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// LVset AFTER the instruction
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterference(const Value *const Def,
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const LiveVarSet *const LVSet,
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const bool isCallInst) {
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LiveVarSet::const_iterator LIt = LVSet->begin();
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// get the live range of instruction
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const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
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IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
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assert( IGNodeOfDef );
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RegClass *const RCOfDef = LROfDef->getRegClass();
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// for each live var in live variable set
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for( ; LIt != LVSet->end(); ++LIt) {
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if( DEBUG_RA > 1) {
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cout << "< Def="; printValue(Def);
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cout << ", Lvar="; printValue( *LIt); cout << "> ";
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}
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// get the live range corresponding to live var
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LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
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// LROfVar can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LROfVar) {
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if(LROfDef == LROfVar) // do not set interf for same LR
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continue;
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// if 2 reg classes are the same set interference
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if( RCOfDef == LROfVar->getRegClass() ){
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RCOfDef->setInterference( LROfDef, LROfVar);
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}
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else if(DEBUG_RA > 1) {
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// we will not have LRs for values not explicitly allocated in the
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// instruction stream (e.g., constants)
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cout << " warning: no live range for " ;
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printValue( *LIt); cout << endl; }
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}
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}
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}
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//----------------------------------------------------------------------------
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// For a call instruction, this method sets the CallInterference flag in
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// the LR of each variable live int the Live Variable Set live after the
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// call instruction (except the return value of the call instruction - since
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// the return value does not interfere with that call itself).
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//----------------------------------------------------------------------------
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void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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const LiveVarSet *const LVSetAft )
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{
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// Now find the LR of the return value of the call
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// We do this because, we look at the LV set *after* the instruction
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// to determine, which LRs must be saved across calls. The return value
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// of the call is live in this set - but it does not interfere with call
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// (i.e., we can allocate a volatile register to the return value)
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LiveRange *RetValLR = NULL;
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const Value *RetVal = MRI.getCallInstRetVal( MInst );
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if( RetVal ) {
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RetValLR = LRI.getLiveRangeForValue( RetVal );
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assert( RetValLR && "No LR for RetValue of call");
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}
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if( DEBUG_RA)
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cout << "\n For call inst: " << *MInst;
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LiveVarSet::const_iterator LIt = LVSetAft->begin();
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// for each live var in live variable set after machine inst
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for( ; LIt != LVSetAft->end(); ++LIt) {
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// get the live range corresponding to live var
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LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
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if( LR && DEBUG_RA) {
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cout << "\n\tLR Aft Call: ";
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LR->printSet();
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}
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// LR can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LR && (LR != RetValLR) ) {
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LR->setCallInterference();
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if( DEBUG_RA) {
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cout << "\n ++Added call interf for LR: " ;
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LR->printSet();
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}
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}
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}
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}
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//----------------------------------------------------------------------------
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// This method will walk thru code and create interferences in the IG of
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// each RegClass.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator
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MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr *const MInst = *MInstIterator;
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// get the LV set after the instruction
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const LiveVarSet *const LVSetAI =
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LVI->getLiveVarSetAfterMInst(MInst, *BBI);
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const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
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if( isCallInst ) {
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//cout << "\nFor call inst: " << *MInst;
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// set the isCallInterference flag of each live range wich extends
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// accross this call instruction. This information is used by graph
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// coloring algo to avoid allocating volatile colors to live ranges
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// that span across calls (since they have to be saved/restored)
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setCallInterferences( MInst, LVSetAI);
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}
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
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if( OpI.isDef() ) {
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// create a new LR iff this operand is a def
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addInterference(*OpI, LVSetAI, isCallInst );
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} //if this is a def
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} // for all operands
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// Also add interference for any implicit definitions in a machine
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// instr (currently, only calls have this).
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unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
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if( NumOfImpRefs > 0 ) {
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for(unsigned z=0; z < NumOfImpRefs; z++)
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if( MInst->implicitRefIsDefined(z) )
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addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
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}
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} // for all machine instructions in BB
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} // for all BBs in method
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// add interferences for method arguments. Since there are no explict
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// defs in method for args, we have to add them manually
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addInterferencesForArgs(); // add interference for method args
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if( DEBUG_RA)
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cout << "Interference graphs calculted!" << endl;
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}
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//----------------------------------------------------------------------------
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// This method will add interferences for incoming arguments to a method.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterferencesForArgs()
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{
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// get the InSet of root BB
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const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
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// get the argument list
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const Method::ArgumentListType& ArgList = Meth->getArgumentList();
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// get an iterator to arg list
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Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
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addInterference( *ArgIt, InSet, false ); // add interferences between
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// args and LVars at start
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if( DEBUG_RA > 1) {
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cout << " - %% adding interference for argument ";
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printValue( (const Value *) *ArgIt); cout << endl;
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}
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}
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}
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#if 0
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//----------------------------------------------------------------------------
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// This method inserts caller saving/restoring instructons before/after
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// a call machine instruction.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
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const BasicBlock *BB )
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{
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// assert( (TM.getInstrInfo()).isCall( MInst->getOpCode() ) );
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StackOffsets.resetTmpPos();
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hash_set<unsigned> PushedRegSet;
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// Now find the LR of the return value of the call
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// The last *implicit operand* is the return value of a call
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// Insert it to to he PushedRegSet since we must not save that register
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// and restore it after the call.
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// We do this because, we look at the LV set *after* the instruction
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// to determine, which LRs must be saved across calls. The return value
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// of the call is live in this set - but we must not save/restore it.
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const Value *RetVal = MRI.getCallInstRetVal( MInst );
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if( RetVal ) {
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LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
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assert( RetValLR && "No LR for RetValue of call");
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PushedRegSet.insert(
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MRI.getUnifiedRegNum((RetValLR->getRegClass())->getID(),
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RetValLR->getColor() ) );
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}
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const LiveVarSet *LVSetAft = LVI->getLiveVarSetAfterMInst(MInst, BB);
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LiveVarSet::const_iterator LIt = LVSetAft->begin();
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// for each live var in live variable set after machine inst
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for( ; LIt != LVSetAft->end(); ++LIt) {
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// get the live range corresponding to live var
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LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
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// LR can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LR ) {
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if( LR->hasColor() ) {
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unsigned RCID = (LR->getRegClass())->getID();
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unsigned Color = LR->getColor();
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if ( MRI.isRegVolatile(RCID, Color) ) {
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// if the value is in both LV sets (i.e., live before and after
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// the call machine instruction)
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unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
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if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
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// if we haven't already pushed that register
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unsigned RegType = MRI.getRegType( LR );
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// Now get two instructions - to push on stack and pop from stack
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// and add them to InstrnsBefore and InstrnsAfter of the
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// call instruction
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int StackOff = StackOffsets.getNewTmpPosOffFromSP();
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/**** TODO
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if( RegType == SaveViaIntReg) {
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int FreeIntReg = getFreedIntReg(......)
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}
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*/
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MachineInstr *AdIBef =
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MRI.cpReg2MemMI(Reg, MRI.getStackPointer(), StackOff, RegType );
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MachineInstr *AdIAft =
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MRI.cpMem2RegMI(MRI.getStackPointer(), StackOff, Reg, RegType );
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((AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
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((AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
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PushedRegSet.insert( Reg );
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if(DEBUG_RA) {
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cerr << "\nFor callee save call inst:" << *MInst;
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cerr << "\n -inserted caller saving instrs:\n\t ";
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cerr << *AdIBef << "\n\t" << *AdIAft ;
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}
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} // if not already pushed
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} // if LR has a volatile color
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} // if LR has color
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} // if there is a LR for Var
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} // for each value in the LV set after instruction
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}
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#endif
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//----------------------------------------------------------------------------
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// This method is called after register allocation is complete to set the
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// allocated reisters in the machine code. This code will add register numbers
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// to MachineOperands that contain a Value.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::updateMachineCode()
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{
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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// get the iterator for machine instructions
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MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *MInst = *MInstIterator;
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// if this machine instr is call, insert caller saving code
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if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
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MRI.insertCallerSavingCode(MInst, *BBI, *this );
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// If there are instructions to be added, *before* this machine
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// instruction, add them now.
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if( AddedInstrMap[ MInst ] ) {
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deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
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if( ! IBef.empty() ) {
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deque<MachineInstr *>::iterator AdIt;
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for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
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if( DEBUG_RA)
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cerr << " *$* PREPENDed instr " << *AdIt << endl;
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MInstIterator = MIVec.insert( MInstIterator, *AdIt );
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++MInstIterator;
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}
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}
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}
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// reset the stack offset for temporary variables since we may
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// need that to spill
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StackOffsets.resetTmpPos();
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister) {
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const Value *const Val = Op.getVRegValue();
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// delete this condition checking later (must assert if Val is null)
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if( !Val) {
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if (DEBUG_RA)
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cout << "Warning: NULL Value found for operand" << endl;
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continue;
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}
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assert( Val && "Value is NULL");
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LiveRange *const LR = LRI.getLiveRangeForValue(Val);
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if ( !LR ) {
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// nothing to worry if it's a const or a label
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if (DEBUG_RA) {
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cout << "*NO LR for operand : " << Op ;
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cout << " [reg:" << Op.getAllocatedRegNum() << "]";
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cout << " in inst:\t" << *MInst << endl;
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}
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// if register is not allocated, mark register as invalid
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if( Op.getAllocatedRegNum() == -1)
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Op.setRegForValue( MRI.getInvalidRegNum());
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continue;
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}
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unsigned RCID = (LR->getRegClass())->getID();
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if( LR->hasColor() ) {
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Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
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}
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else {
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// LR did NOT receive a color (register). Now, insert spill code
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// for spilled opeands in this machine instruction
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assert(0 && "LR must be spilled");
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// insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
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}
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}
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} // for each operand
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|
|
|
|
// If there are instructions to be added *after* this machine
|
|
// instruction, add them now
|
|
|
|
if( AddedInstrMap[ MInst ] &&
|
|
! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
|
|
|
|
// if there are delay slots for this instruction, the instructions
|
|
// added after it must really go after the delayed instruction(s)
|
|
// So, we move the InstrAfter of the current instruction to the
|
|
// corresponding delayed instruction
|
|
|
|
unsigned delay;
|
|
if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
|
|
move2DelayedInstr(MInst, *(MInstIterator+delay) );
|
|
|
|
if(DEBUG_RA) cout<< "\nMoved an added instr after the delay slot";
|
|
}
|
|
|
|
else {
|
|
|
|
|
|
// Here we can add the "instructions after" to the current
|
|
// instruction since there are no delay slots for this instruction
|
|
|
|
deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
|
|
|
|
if( ! IAft.empty() ) {
|
|
|
|
deque<MachineInstr *>::iterator AdIt;
|
|
|
|
++MInstIterator; // advance to the next instruction
|
|
|
|
for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
|
|
|
|
if(DEBUG_RA)
|
|
cerr << " *#* APPENDed instr opcode: " << *AdIt << endl;
|
|
|
|
MInstIterator = MIVec.insert( MInstIterator, *AdIt );
|
|
++MInstIterator;
|
|
}
|
|
|
|
// MInsterator already points to the next instr. Since the
|
|
// for loop also increments it, decrement it to point to the
|
|
// instruction added last
|
|
--MInstIterator;
|
|
|
|
}
|
|
|
|
} // if not delay
|
|
|
|
}
|
|
|
|
} // for each machine instruction
|
|
}
|
|
}
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method inserts spill code for AN operand whose LR was spilled.
|
|
// This method may be called several times for a single machine instruction
|
|
// if it contains many spilled operands. Each time it is called, it finds
|
|
// a register which is not live at that instruction and also which is not
|
|
// used by other spilled operands of the same instruction. Then it uses
|
|
// this register temporarily to accomodate the spilled value.
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
|
|
const MachineInstr *MInst,
|
|
const BasisBlock *BB,
|
|
const unsigned OpNum) {
|
|
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
bool isDef = MInst->operandIsDefined(OpNum);
|
|
unsigned RegType = MRI.getRegType( LR );
|
|
int SpillOff = LR->getSpillOffFromFP();
|
|
RegClass *RC = LR->getRegClass();
|
|
const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
|
|
int TmpOff = StackOffsets.getNewTmpPosOffFromSP();
|
|
MachineInstr *MIBef, *AdIMid, *MIAft;
|
|
int TmpReg;
|
|
|
|
TmpReg = getUsableRegAtMI(RC, RegType, MInst,LVSetBef, MIBef, MIAft);
|
|
TmpReg = getUnifiedRegNum( RC->getID(), TmpReg );
|
|
|
|
|
|
if( !isDef ) {
|
|
|
|
// for a USE, we have to load the value of LR from stack to a TmpReg
|
|
// and use the TmpReg as one operand of instruction
|
|
|
|
// actual loading instruction
|
|
AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpReg, RegType);
|
|
|
|
if( MIBef )
|
|
((AddedInstrMap[MInst])->InstrnsBefore).push_back(MIBef);
|
|
|
|
((AddedInstrMap[MInst])->InstrnsBefore).push_back(AdiMid);
|
|
|
|
if( MIAft)
|
|
((AddedInstrMap[MInst])->InstrnsAfter).push_front(MIAft);
|
|
|
|
|
|
}
|
|
else { // if this is a Def
|
|
|
|
// for a DEF, we have to store the value produced by this instruction
|
|
// on the stack position allocated for this LR
|
|
|
|
// actual storing instruction
|
|
AdIMid = MRI.cpReg2MemMI(TmpReg, MRI.getFramePointer(), SpillOff, RegType);
|
|
|
|
if( MIBef )
|
|
((AddedInstrMap[MInst])->InstrnsBefore).push_back(MIBef);
|
|
|
|
((AddedInstrMap[MInst])->InstrnsBefore).push_back(AdiMid);
|
|
|
|
if( MIAft)
|
|
((AddedInstrMap[MInst])->InstrnsAfter).push_front(MIAft);
|
|
|
|
} // if !DEF
|
|
|
|
|
|
Op.setRegForValue( TmpReg ); // set the opearnd
|
|
|
|
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// We can use the following method to get a temporary register to be used
|
|
// BEFORE any given machine instruction. If there is a register available,
|
|
// this method will simply return that register and set MIBef = MIAft = NULL.
|
|
// Otherwise, it will return a register and MIAft and MIBef will contain
|
|
// two instructions used to free up this returned register.
|
|
//----------------------------------------------------------------------------
|
|
|
|
int PhyRegAlloc::getUsableRegAtMI(const RegClass *RC,
|
|
const int RegType,
|
|
const MachineInstr *MInst,
|
|
const LiveVarSet *LVSetBef,
|
|
MachineInstr *MIBef,
|
|
MachineInstr *MIAft) {
|
|
|
|
int Reg = getUnusedRegAtMI(RC, MInst, LVSetBef);
|
|
|
|
if( Reg != -1) {
|
|
// we found an unused register, so we can simply used
|
|
MIBef = MIAft = NULL;
|
|
}
|
|
else {
|
|
// we couldn't find an unused register. Generate code to ree up a reg by
|
|
// saving it on stack and restoring after the instruction
|
|
|
|
Reg = getRegNotUsedByThisInst(RC, MInst);
|
|
MIBef = cpReg2MemMI(Reg, MRI.getFramePointer(), TmpOff, RegType );
|
|
MIAft = cpMem2RegMI(MEI.getFramePointer(), TmpOff, Reg, RegType );
|
|
}
|
|
|
|
return Reg;
|
|
}
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method is called to get a new unused register that can be used to
|
|
// accomodate a spilled value.
|
|
// This method may be called several times for a single machine instruction
|
|
// if it contains many spilled operands. Each time it is called, it finds
|
|
// a register which is not live at that instruction and also which is not
|
|
// used by other spilled operands of the same instruction.
|
|
//----------------------------------------------------------------------------
|
|
int PhyRegAlloc::getUnusedRegAtMI(const RegClass *RC,
|
|
const MachineInstr *MInst,
|
|
const LiveVarSet *LVSetBef) {
|
|
|
|
unsigned NumAvailRegs = RC->getNumOfAvailRegs();
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
|
|
for(unsigned i=0; i < NumAvailRegs; i++);
|
|
IsColorUsedArr[i] = false;
|
|
|
|
LiveVarSet::const_iterator LIt = LVSetBef->begin();
|
|
|
|
// for each live var in live variable set after machine inst
|
|
for( ; LIt != LVSetBef->end(); ++LIt) {
|
|
|
|
// get the live range corresponding to live var
|
|
LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
|
|
|
|
// LR can be null if it is a const since a const
|
|
// doesn't have a dominating def - see Assumptions above
|
|
if( LRofLV )
|
|
if( LRofLV->hasColor() )
|
|
IsColorUsedArr[ LRofLV->getColor() ] = true;
|
|
}
|
|
|
|
// It is possible that one operand of this MInst was already spilled
|
|
// and it received some register temporarily. If that's the case,
|
|
// it is recorded in machine operand. We must skip such registers.
|
|
|
|
setRegsUsedByThisInst(RC, MInst);
|
|
|
|
unsigned c; // find first unused color
|
|
for( c=0; c < NumAvailRegs; c++)
|
|
if( ! IsColorUsedArr[ c ] ) break;
|
|
|
|
if(c < NumAvailRegs)
|
|
return c;
|
|
else
|
|
return -1;
|
|
|
|
|
|
}
|
|
|
|
|
|
#endif
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method modifies the IsColorUsedArr of the register class passed to it.
|
|
// It sets the bits corresponding to the registers used by this machine
|
|
// instructions. Explicit operands are set.
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::setRegsUsedByThisInst(RegClass *RC,
|
|
const MachineInstr *MInst ) {
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
|
|
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
|
|
const MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
Op.getOperandType() == MachineOperand::MO_CCRegister) {
|
|
|
|
const Value *const Val = Op.getVRegValue();
|
|
|
|
if( !Val )
|
|
if( MRI.getRegClassIDOfValue( Val )== RC->getID() ) {
|
|
int Reg;
|
|
if( (Reg=Op.getAllocatedRegNum()) != -1)
|
|
IsColorUsedArr[ Reg ] = true;
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
// If there are implicit references, mark them as well
|
|
|
|
for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
|
|
|
|
LiveRange *const LRofImpRef =
|
|
LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
|
|
|
|
if( LRofImpRef )
|
|
if( LRofImpRef->hasColor() )
|
|
IsColorUsedArr[ LRofImpRef->getColor() ] = true;
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// Get any other register in a register class, other than what is used
|
|
// by operands of a machine instruction.
|
|
//----------------------------------------------------------------------------
|
|
int PhyRegAlloc::getRegNotUsedByThisInst(RegClass *RC,
|
|
const MachineInstr *MInst) {
|
|
|
|
bool *IsColorUsedArr = RC->getIsColorUsedArr();
|
|
unsigned NumAvailRegs = RC->getNumOfAvailRegs();
|
|
|
|
|
|
for(unsigned i=0; i < NumAvailRegs ; i++)
|
|
IsColorUsedArr[i] = false;
|
|
|
|
setRegsUsedByThisInst(RC, MInst);
|
|
|
|
unsigned c; // find first unused color
|
|
for( c=0; c < RC->getNumOfAvailRegs(); c++)
|
|
if( ! IsColorUsedArr[ c ] ) break;
|
|
|
|
if(c < NumAvailRegs)
|
|
return c;
|
|
else
|
|
assert( 0 && "FATAL: No free register could be found in reg class!!");
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// If there are delay slots for an instruction, the instructions
|
|
// added after it must really go after the delayed instruction(s).
|
|
// So, we move the InstrAfter of that instruction to the
|
|
// corresponding delayed instruction using the following method.
|
|
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
|
|
const MachineInstr *DelayedMI) {
|
|
|
|
|
|
// "added after" instructions of the original instr
|
|
deque<MachineInstr *> &OrigAft = (AddedInstrMap[OrigMI])->InstrnsAfter;
|
|
|
|
// "added instructions" of the delayed instr
|
|
AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
|
|
|
|
if(! DelayAdI ) { // create a new "added after" if necessary
|
|
DelayAdI = new AddedInstrns();
|
|
AddedInstrMap[DelayedMI] = DelayAdI;
|
|
}
|
|
|
|
// "added after" instructions of the delayed instr
|
|
deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
|
|
|
|
// go thru all the "added after instructions" of the original instruction
|
|
// and append them to the "addded after instructions" of the delayed
|
|
// instructions
|
|
|
|
deque<MachineInstr *>::iterator OrigAdIt;
|
|
|
|
for( OrigAdIt = OrigAft.begin(); OrigAdIt != OrigAft.end() ; ++OrigAdIt ) {
|
|
DelayedAft.push_back( *OrigAdIt );
|
|
}
|
|
|
|
// empty the "added after instructions" of the original instruction
|
|
OrigAft.clear();
|
|
|
|
}
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method prints the code with registers after register allocation is
|
|
// complete.
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::printMachineCode()
|
|
{
|
|
|
|
cout << endl << ";************** Method ";
|
|
cout << Meth->getName() << " *****************" << endl;
|
|
|
|
Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
|
|
|
|
for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
|
|
|
|
cout << endl ; printLabel( *BBI); cout << ": ";
|
|
|
|
// get the iterator for machine instructions
|
|
MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
|
MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
|
|
|
|
// iterate over all the machine instructions in BB
|
|
for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
|
|
|
|
MachineInstr *const MInst = *MInstIterator;
|
|
|
|
|
|
cout << endl << "\t";
|
|
cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
|
|
|
|
|
//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
|
|
|
|
for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
|
|
if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
|
Op.getOperandType() == MachineOperand::MO_CCRegister /*||
|
|
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
|
|
|
|
const Value *const Val = Op.getVRegValue () ;
|
|
// ****this code is temporary till NULL Values are fixed
|
|
if( ! Val ) {
|
|
cout << "\t<*NULL*>";
|
|
continue;
|
|
}
|
|
|
|
// if a label or a constant
|
|
if( (Val->getValueType() == Value::BasicBlockVal) ) {
|
|
|
|
cout << "\t"; printLabel( Op.getVRegValue () );
|
|
}
|
|
else {
|
|
// else it must be a register value
|
|
const int RegNum = Op.getAllocatedRegNum();
|
|
|
|
cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
|
|
}
|
|
|
|
}
|
|
else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
|
cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
|
|
}
|
|
|
|
else
|
|
cout << "\t" << Op; // use dump field
|
|
}
|
|
|
|
|
|
|
|
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
|
|
if( NumOfImpRefs > 0 ) {
|
|
|
|
cout << "\tImplicit:";
|
|
|
|
for(unsigned z=0; z < NumOfImpRefs; z++) {
|
|
printValue( MInst->getImplicitRef(z) );
|
|
cout << "\t";
|
|
}
|
|
|
|
}
|
|
|
|
} // for all machine instructions
|
|
|
|
|
|
cout << endl;
|
|
|
|
} // for all BBs
|
|
|
|
cout << endl;
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
//
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::colorCallRetArgs()
|
|
{
|
|
|
|
CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
|
|
CallRetInstrListType::const_iterator It = CallRetInstList.begin();
|
|
|
|
for( ; It != CallRetInstList.end(); ++It ) {
|
|
|
|
const MachineInstr *const CRMI = *It;
|
|
unsigned OpCode = CRMI->getOpCode();
|
|
|
|
// get the added instructions for this Call/Ret instruciton
|
|
AddedInstrns *AI = AddedInstrMap[ CRMI ];
|
|
if ( !AI ) {
|
|
AI = new AddedInstrns();
|
|
AddedInstrMap[ CRMI ] = AI;
|
|
}
|
|
|
|
// Tmp stack poistions are needed by some calls that have spilled args
|
|
// So reset it before we call each such method
|
|
StackOffsets.resetTmpPos();
|
|
|
|
if( (TM.getInstrInfo()).isCall( OpCode ) )
|
|
MRI.colorCallArgs( CRMI, LRI, AI, *this );
|
|
|
|
else if ( (TM.getInstrInfo()).isReturn(OpCode) )
|
|
MRI.colorRetValue( CRMI, LRI, AI );
|
|
|
|
else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::colorIncomingArgs()
|
|
{
|
|
const BasicBlock *const FirstBB = Meth->front();
|
|
const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
|
|
assert( FirstMI && "No machine instruction in entry BB");
|
|
|
|
AddedInstrns *AI = AddedInstrMap[ FirstMI ];
|
|
if ( !AI ) {
|
|
AI = new AddedInstrns();
|
|
AddedInstrMap[ FirstMI ] = AI;
|
|
}
|
|
|
|
MRI.colorMethodArgs(Meth, LRI, AI );
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// Used to generate a label for a basic block
|
|
//----------------------------------------------------------------------------
|
|
void PhyRegAlloc::printLabel(const Value *const Val)
|
|
{
|
|
if( Val->hasName() )
|
|
cout << Val->getName();
|
|
else
|
|
cout << "Label" << Val;
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method calls setSugColorUsable method of each live range. This
|
|
// will determine whether the suggested color of LR is really usable.
|
|
// A suggested color is not usable when the suggested color is volatile
|
|
// AND when there are call interferences
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::markUnusableSugColors()
|
|
{
|
|
if(DEBUG_RA ) cout << "\nmarking unusable suggested colors ..." << endl;
|
|
|
|
// hash map iterator
|
|
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
|
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
|
|
|
for( ; HMI != HMIEnd ; ++HMI ) {
|
|
|
|
if( (*HMI).first ) {
|
|
|
|
LiveRange *L = (*HMI).second; // get the LiveRange
|
|
|
|
if(L) {
|
|
if( L->hasSuggestedColor() ) {
|
|
|
|
int RCID = (L->getRegClass())->getID();
|
|
if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
|
|
L->isCallInterference() )
|
|
L->setSuggestedColorUsable( false );
|
|
else
|
|
L->setSuggestedColorUsable( true );
|
|
}
|
|
} // if L->hasSuggestedColor()
|
|
}
|
|
} // for all LR's in hash map
|
|
}
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// The following method will set the stack offsets of the live ranges that
|
|
// are decided to be spillled. This must be called just after coloring the
|
|
// LRs using the graph coloring algo. For each live range that is spilled,
|
|
// this method allocate a new spill position on the stack.
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::allocateStackSpace4SpilledLRs()
|
|
{
|
|
if(DEBUG_RA ) cout << "\nsetting LR stack offsets ..." << endl;
|
|
|
|
// hash map iterator
|
|
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
|
|
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
|
|
|
for( ; HMI != HMIEnd ; ++HMI ) {
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|
|
|
if( (*HMI).first ) {
|
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LiveRange *L = (*HMI).second; // get the LiveRange
|
|
if(L)
|
|
if( ! L->hasColor() )
|
|
L->setSpillOffFromFP( StackOffsets.getNewSpillOffFromFP() );
|
|
}
|
|
} // for all LR's in hash map
|
|
|
|
StackOffsets.setEndOfSpillRegion();
|
|
|
|
}
|
|
|
|
|
|
|
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|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// The entry pont to Register Allocation
|
|
//----------------------------------------------------------------------------
|
|
|
|
void PhyRegAlloc::allocateRegisters()
|
|
{
|
|
|
|
// make sure that we put all register classes into the RegClassList
|
|
// before we call constructLiveRanges (now done in the constructor of
|
|
// PhyRegAlloc class).
|
|
|
|
constructLiveRanges(); // create LR info
|
|
|
|
if( DEBUG_RA )
|
|
LRI.printLiveRanges();
|
|
|
|
createIGNodeListsAndIGs(); // create IGNode list and IGs
|
|
|
|
buildInterferenceGraphs(); // build IGs in all reg classes
|
|
|
|
|
|
if( DEBUG_RA ) {
|
|
// print all LRs in all reg classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIGNodeList();
|
|
|
|
// print IGs in all register classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIG();
|
|
}
|
|
|
|
LRI.coalesceLRs(); // coalesce all live ranges
|
|
|
|
if( DEBUG_RA) {
|
|
// print all LRs in all reg classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIGNodeList();
|
|
|
|
// print IGs in all register classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIG();
|
|
}
|
|
|
|
|
|
// mark un-usable suggested color before graph coloring algorithm.
|
|
// When this is done, the graph coloring algo will not reserve
|
|
// suggested color unnecessarily - they can be used by another LR
|
|
markUnusableSugColors();
|
|
|
|
// color all register classes using the graph coloring algo
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->colorAllRegs();
|
|
|
|
// Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
|
|
// a poistion for such spilled LRs
|
|
allocateStackSpace4SpilledLRs();
|
|
|
|
// color incoming args and call args
|
|
colorIncomingArgs();
|
|
colorCallRetArgs();
|
|
|
|
|
|
updateMachineCode();
|
|
if (DEBUG_RA) {
|
|
Meth->getMachineCode().dump();
|
|
printMachineCode(); // only for DEBUGGING
|
|
}
|
|
}
|
|
|
|
|
|
|