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176d1faf6a
llvm-6502/test/CodeGen
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Jan Vesely 176d1faf6a R600: Use SIGN_EXTEND_INREG for SEXT loads 
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238229 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-26 18:07:22 +00:00
..
AArch64 Revert "Re-commit changes in r237579 with fix for bug breaking windows builds." 2015-05-26 17:45:38 +00:00
ARM Revert "Re-commit changes in r237579 with fix for bug breaking windows builds." 2015-05-26 17:45:38 +00:00
BPF
CPP
Generic Revert r237954, "Resubmit r237708 (MIR Serialization: print and parse LLVM IR using MIR format)." 2015-05-22 07:17:07 +00:00
Hexagon [Hexagon] Generate hardware loop for a vectorized loop 2015-05-14 20:36:19 +00:00
Inputs
Mips [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only. 2015-05-26 10:19:18 +00:00
MSP430
NVPTX
PowerPC This patch adds support for the vector quadword add/sub instructions introduced 2015-05-25 15:49:26 +00:00
R600 R600: Use SIGN_EXTEND_INREG for SEXT loads 2015-05-26 18:07:22 +00:00
SPARC Add support for the Sparc implementation-defined "ASR" registers. 2015-05-18 16:29:48 +00:00
SystemZ
Thumb
Thumb2 Revert r237590, "ARM: allow jump tables to be placed as constant islands." 2015-05-21 23:20:55 +00:00
WinEH [WinEH] C++ EH state numbering fixes 2015-05-20 23:22:24 +00:00
X86 AVX-512: fixed a bug in lowering VSELECT for 512-bit vector 2015-05-26 11:32:39 +00:00
XCore