llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-06 14:57:41 +00:00

History

Bill Wendling 98a366d547 Instead of passing in an unsigned value for the optimization level, use an enum, which better identifies what the optimization is doing. And is more flexible for future uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8		2009-04-29 23:29:43 +00:00
..
AsmPrinter	Instead of passing in an unsigned value for the optimization level, use an enum,	2009-04-29 23:29:43 +00:00
CMakeLists.txt
DelaySlotFiller.cpp	Remove non-DebugLoc versions of buildMI from Sparc.	2009-02-13 02:31:35 +00:00
FPMover.cpp	Add explicit keywords.	2009-02-18 16:37:45 +00:00
Makefile
README.txt
Sparc.h	Instead of passing in an unsigned value for the optimization level, use an enum,	2009-04-29 23:29:43 +00:00
Sparc.td
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp	Factor out the code to add a MachineOperand to a MachineInstrBuilder.	2009-02-18 05:45:50 +00:00
SparcInstrInfo.h
SparcInstrInfo.td
SparcISelDAGToDAG.cpp	Eliminate remaining non-DebugLoc version of getTargetNode.	2009-02-06 19:16:40 +00:00
SparcISelLowering.cpp	Remove non-DebugLoc versions of buildMI from Sparc.	2009-02-13 02:31:35 +00:00
SparcISelLowering.h	Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing	2009-02-07 16:15:20 +00:00
SparcRegisterInfo.cpp	Propagate debug loc info through prologue/epilogue.	2009-02-23 00:42:30 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetAsmInfo.cpp
SparcTargetAsmInfo.h
SparcTargetMachine.cpp	Instead of passing in an unsigned value for the optimization level, use an enum,	2009-04-29 23:29:43 +00:00
SparcTargetMachine.h	Instead of passing in an unsigned value for the optimization level, use an enum,	2009-04-29 23:29:43 +00:00

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots