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https://github.com/c64scene-ar/llvm-6502.git
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b3cabb44c3
RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
227 lines
6.6 KiB
LLVM
227 lines
6.6 KiB
LLVM
; Test 8-bit atomic min/max operations.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2
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; Check signed minimum.
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; - CHECK is for the main loop.
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; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
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; RLL is set up correctly. The negation is independent of the NILL and L
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; tested in CHECK.
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; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
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; before being used, and that the low bits are set to 1. This sequence is
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; independent of the other loop prologue instructions.
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define i8 @f1(i8 *%src, i8 %b) {
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; CHECK: f1:
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; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
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; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
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; CHECK: risbg [[ROT]], %r3, 32, 39, 0
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; CHECK: [[KEEP]]:
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
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; CHECK: jlh [[LOOP]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f1:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2: f1:
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; CHECK-SHIFT2: sll %r3, 24
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw min i8 *%src, i8 %b seq_cst
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ret i8 %res
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}
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; Check signed maximum.
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define i8 @f2(i8 *%src, i8 %b) {
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; CHECK: f2:
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; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
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; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
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; CHECK: risbg [[ROT]], %r3, 32, 39, 0
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; CHECK: [[KEEP]]:
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
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; CHECK: jlh [[LOOP]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f2:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2: f2:
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; CHECK-SHIFT2: sll %r3, 24
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw max i8 *%src, i8 %b seq_cst
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ret i8 %res
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}
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; Check unsigned minimum.
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define i8 @f3(i8 *%src, i8 %b) {
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; CHECK: f3:
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; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
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; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: clr [[ROT]], %r3
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; CHECK: jle [[KEEP:\..*]]
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; CHECK: risbg [[ROT]], %r3, 32, 39, 0
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; CHECK: [[KEEP]]:
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
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; CHECK: jlh [[LOOP]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f3:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2: f3:
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; CHECK-SHIFT2: sll %r3, 24
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw umin i8 *%src, i8 %b seq_cst
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ret i8 %res
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}
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; Check unsigned maximum.
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define i8 @f4(i8 *%src, i8 %b) {
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; CHECK: f4:
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; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
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; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: clr [[ROT]], %r3
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; CHECK: jhe [[KEEP:\..*]]
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; CHECK: risbg [[ROT]], %r3, 32, 39, 0
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; CHECK: [[KEEP]]:
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
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; CHECK: jlh [[LOOP]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f4:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2: f4:
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; CHECK-SHIFT2: sll %r3, 24
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw umax i8 *%src, i8 %b seq_cst
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ret i8 %res
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}
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; Check the lowest useful signed minimum value. We need to load 0x81000000
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; into the source register.
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define i8 @f5(i8 *%src) {
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; CHECK: f5:
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; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
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; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
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; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f5:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2: f5:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw min i8 *%src, i8 -127 seq_cst
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ret i8 %res
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}
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; Check the highest useful signed maximum value. We need to load 0x7e000000
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; into the source register.
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define i8 @f6(i8 *%src) {
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; CHECK: f6:
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; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
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; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
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; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f6:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2: f6:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw max i8 *%src, i8 126 seq_cst
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ret i8 %res
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}
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; Check the lowest useful unsigned minimum value. We need to load 0x01000000
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; into the source register.
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define i8 @f7(i8 *%src) {
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; CHECK: f7:
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; CHECK: llilh [[SRC2:%r[0-9]+]], 256
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; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
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; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f7:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2: f7:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw umin i8 *%src, i8 1 seq_cst
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ret i8 %res
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}
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; Check the highest useful unsigned maximum value. We need to load 0xfe000000
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; into the source register.
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define i8 @f8(i8 *%src) {
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; CHECK: f8:
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; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
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; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
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; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f8:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2: f8:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw umax i8 *%src, i8 254 seq_cst
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ret i8 %res
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}
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