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https://github.com/c64scene-ar/llvm-6502.git
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9bcad42c3a
Normal (sext (setcc ...)) sequences are optimised into (select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND. However, this is deliberately not done for vectors, and after vector type legalization we have (sext_inreg (setcc ...)) instead. I wondered about trying to extend DAGCombiner to handle this case too, but it seemed to be a loss on some other targets I tried, even those for which SETCC isn't "legal" and SELECT_CC is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186149 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
3.6 KiB
LLVM
160 lines
3.6 KiB
LLVM
; Test all condition-code masks that are relevant for CGRJ.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @foo()
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; Test EQ.
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define void @f1(i64 %target) {
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; CHECK: f1:
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; CHECK: .cfi_def_cfa_offset
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; CHECK: .L[[LABEL:.*]]:
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; CHECK: cgrje %r2, {{%r[0-9]+}}, .L[[LABEL]]
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br label %loop
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loop:
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%val = call i64 @foo()
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%cond = icmp eq i64 %val, %target
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; Test NE.
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define void @f2(i64 %target) {
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; CHECK: f2:
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; CHECK: .cfi_def_cfa_offset
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; CHECK: .L[[LABEL:.*]]:
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; CHECK: cgrjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
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br label %loop
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loop:
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%val = call i64 @foo()
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%cond = icmp ne i64 %val, %target
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; Test SLE.
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define void @f3(i64 %target) {
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; CHECK: f3:
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; CHECK: .cfi_def_cfa_offset
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; CHECK: .L[[LABEL:.*]]:
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; CHECK: cgrjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
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br label %loop
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loop:
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%val = call i64 @foo()
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%cond = icmp sle i64 %val, %target
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; Test SLT.
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define void @f4(i64 %target) {
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; CHECK: f4:
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; CHECK: .cfi_def_cfa_offset
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; CHECK: .L[[LABEL:.*]]:
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; CHECK: cgrjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
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br label %loop
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loop:
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%val = call i64 @foo()
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%cond = icmp slt i64 %val, %target
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; Test SGT.
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define void @f5(i64 %target) {
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; CHECK: f5:
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; CHECK: .cfi_def_cfa_offset
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; CHECK: .L[[LABEL:.*]]:
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; CHECK: cgrjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
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br label %loop
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loop:
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%val = call i64 @foo()
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%cond = icmp sgt i64 %val, %target
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; Test SGE.
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define void @f6(i64 %target) {
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; CHECK: f6:
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; CHECK: .cfi_def_cfa_offset
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; CHECK: .L[[LABEL:.*]]:
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; CHECK: cgrjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
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br label %loop
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loop:
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%val = call i64 @foo()
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%cond = icmp sge i64 %val, %target
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; Test a vector of 0/-1 results for i32 EQ.
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define i64 @f7(i64 %a, i64 %b) {
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; CHECK: f7:
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; CHECK: lhi [[REG:%r[0-5]]], -1
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; CHECK: crje {{%r[0-5]}}
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; CHECK: lhi [[REG]], 0
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; CHECK-NOT: sra
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; CHECK: br %r14
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%avec = bitcast i64 %a to <2 x i32>
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%bvec = bitcast i64 %b to <2 x i32>
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%cmp = icmp eq <2 x i32> %avec, %bvec
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%ext = sext <2 x i1> %cmp to <2 x i32>
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%ret = bitcast <2 x i32> %ext to i64
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ret i64 %ret
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}
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; Test a vector of 0/-1 results for i32 NE.
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define i64 @f8(i64 %a, i64 %b) {
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; CHECK: f8:
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; CHECK: lhi [[REG:%r[0-5]]], -1
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; CHECK: crjlh {{%r[0-5]}}
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; CHECK: lhi [[REG]], 0
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; CHECK-NOT: sra
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; CHECK: br %r14
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%avec = bitcast i64 %a to <2 x i32>
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%bvec = bitcast i64 %b to <2 x i32>
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%cmp = icmp ne <2 x i32> %avec, %bvec
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%ext = sext <2 x i1> %cmp to <2 x i32>
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%ret = bitcast <2 x i32> %ext to i64
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ret i64 %ret
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}
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; Test a vector of 0/-1 results for i64 EQ.
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define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
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; CHECK: f9:
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; CHECK: lghi [[REG:%r[0-5]]], -1
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; CHECK: crje {{%r[0-5]}}
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; CHECK: lghi [[REG]], 0
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; CHECK-NOT: sra
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; CHECK: br %r14
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%avec = bitcast i64 %a to <2 x i32>
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%bvec = bitcast i64 %b to <2 x i32>
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%cmp = icmp eq <2 x i32> %avec, %bvec
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%ext = sext <2 x i1> %cmp to <2 x i64>
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store <2 x i64> %ext, <2 x i64> *%dest
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ret void
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}
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; Test a vector of 0/-1 results for i64 NE.
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define void @f10(i64 %a, i64 %b, <2 x i64> *%dest) {
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; CHECK: f10:
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; CHECK: lghi [[REG:%r[0-5]]], -1
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; CHECK: crjlh {{%r[0-5]}}
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; CHECK: lghi [[REG]], 0
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; CHECK-NOT: sra
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; CHECK: br %r14
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%avec = bitcast i64 %a to <2 x i32>
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%bvec = bitcast i64 %b to <2 x i32>
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%cmp = icmp ne <2 x i32> %avec, %bvec
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%ext = sext <2 x i1> %cmp to <2 x i64>
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store <2 x i64> %ext, <2 x i64> *%dest
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ret void
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}
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