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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181706 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
6.5 KiB
C++
225 lines
6.5 KiB
C++
//===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// \brief The R600 code emitter produces machine code that can be executed
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/// directly on the GPU device.
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//
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//===----------------------------------------------------------------------===//
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#include "R600Defines.h"
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#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#include <stdio.h>
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using namespace llvm;
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namespace {
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class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
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R600MCCodeEmitter(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
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void operator=(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
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const MCInstrInfo &MCII;
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const MCRegisterInfo &MRI;
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public:
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R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
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: MCII(mcii), MRI(mri) { }
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/// \brief Encode the instruction and write it to the OS.
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virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// \returns the encoding for an MCOperand.
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virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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private:
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void EmitByte(unsigned int byte, raw_ostream &OS) const;
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void Emit(uint32_t value, raw_ostream &OS) const;
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void Emit(uint64_t value, raw_ostream &OS) const;
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unsigned getHWRegChan(unsigned reg) const;
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unsigned getHWReg(unsigned regNo) const;
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};
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} // End anonymous namespace
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enum RegElement {
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ELEMENT_X = 0,
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ELEMENT_Y,
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ELEMENT_Z,
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ELEMENT_W
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};
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enum FCInstr {
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FC_IF_PREDICATE = 0,
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FC_ELSE,
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FC_ENDIF,
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FC_BGNLOOP,
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FC_ENDLOOP,
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FC_BREAK_PREDICATE,
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FC_CONTINUE
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};
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enum TextureTypes {
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TEXTURE_1D = 1,
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TEXTURE_2D,
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TEXTURE_3D,
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TEXTURE_CUBE,
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TEXTURE_RECT,
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TEXTURE_SHADOW1D,
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TEXTURE_SHADOW2D,
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TEXTURE_SHADOWRECT,
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TEXTURE_1D_ARRAY,
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TEXTURE_2D_ARRAY,
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TEXTURE_SHADOW1D_ARRAY,
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TEXTURE_SHADOW2D_ARRAY
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};
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MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI) {
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return new R600MCCodeEmitter(MCII, MRI);
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}
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void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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if (MI.getOpcode() == AMDGPU::RETURN ||
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MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
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MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
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MI.getOpcode() == AMDGPU::BUNDLE ||
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MI.getOpcode() == AMDGPU::KILL) {
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return;
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} else if (IS_VTX(Desc)) {
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uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
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uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
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InstWord2 |= 1 << 19;
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Emit(InstWord01, OS);
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Emit(InstWord2, OS);
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Emit((u_int32_t) 0, OS);
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} else if (IS_TEX(Desc)) {
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unsigned Opcode = MI.getOpcode();
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bool HasOffsets = (Opcode == AMDGPU::TEX_LD);
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unsigned OpOffset = HasOffsets ? 3 : 0;
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int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
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int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
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uint32_t SrcSelect[4] = {0, 1, 2, 3};
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uint32_t Offsets[3] = {0, 0, 0};
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uint64_t CoordType[4] = {1, 1, 1, 1};
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if (HasOffsets)
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for (unsigned i = 0; i < 3; i++) {
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int SignedOffset = MI.getOperand(i + 2).getImm();
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Offsets[i] = (SignedOffset & 0x1F);
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}
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if (TextureType == TEXTURE_RECT ||
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TextureType == TEXTURE_SHADOWRECT) {
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CoordType[ELEMENT_X] = 0;
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CoordType[ELEMENT_Y] = 0;
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}
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if (TextureType == TEXTURE_1D_ARRAY ||
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TextureType == TEXTURE_SHADOW1D_ARRAY) {
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if (Opcode == AMDGPU::TEX_SAMPLE_C_L ||
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Opcode == AMDGPU::TEX_SAMPLE_C_LB) {
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CoordType[ELEMENT_Y] = 0;
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} else {
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CoordType[ELEMENT_Z] = 0;
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SrcSelect[ELEMENT_Z] = ELEMENT_Y;
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}
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} else if (TextureType == TEXTURE_2D_ARRAY ||
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TextureType == TEXTURE_SHADOW2D_ARRAY) {
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CoordType[ELEMENT_Z] = 0;
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}
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if ((TextureType == TEXTURE_SHADOW1D ||
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TextureType == TEXTURE_SHADOW2D ||
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TextureType == TEXTURE_SHADOWRECT ||
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TextureType == TEXTURE_SHADOW1D_ARRAY) &&
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Opcode != AMDGPU::TEX_SAMPLE_C_L &&
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Opcode != AMDGPU::TEX_SAMPLE_C_LB) {
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SrcSelect[ELEMENT_W] = ELEMENT_Z;
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}
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uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups) |
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CoordType[ELEMENT_X] << 60 | CoordType[ELEMENT_Y] << 61 |
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CoordType[ELEMENT_Z] << 62 | CoordType[ELEMENT_W] << 63;
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uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
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SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
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SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
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Offsets[2] << 10;
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Emit(Word01, OS);
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Emit(Word2, OS);
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Emit((u_int32_t) 0, OS);
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} else {
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uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
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Emit(Inst, OS);
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}
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}
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void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
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OS.write((uint8_t) Byte & 0xff);
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}
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void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
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for (unsigned i = 0; i < 4; i++) {
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OS.write((uint8_t) ((Value >> (8 * i)) & 0xff));
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}
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}
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void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
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for (unsigned i = 0; i < 8; i++) {
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EmitByte((Value >> (8 * i)) & 0xff, OS);
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}
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}
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unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
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return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
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}
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unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
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return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
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}
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uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixup) const {
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if (MO.isReg()) {
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if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
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return MRI.getEncodingValue(MO.getReg());
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} else {
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return getHWReg(MO.getReg());
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}
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} else if (MO.isImm()) {
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return MO.getImm();
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} else {
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assert(0);
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return 0;
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}
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}
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#include "AMDGPUGenMCCodeEmitter.inc"
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