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https://github.com/c64scene-ar/llvm-6502.git
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d04a8d4b33
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
123 lines
4.1 KiB
C++
123 lines
4.1 KiB
C++
//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SPARC implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcRegisterInfo.h"
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#include "Sparc.h"
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#include "SparcSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Type.h"
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#define GET_REGINFO_TARGET_DESC
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#include "SparcGenRegisterInfo.inc"
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using namespace llvm;
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SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
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const TargetInstrInfo &tii)
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: SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
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}
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const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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static const uint16_t CalleeSavedRegs[] = { 0 };
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return CalleeSavedRegs;
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}
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BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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// FIXME: G1 reserved for now for large imm generation by frame code.
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Reserved.set(SP::G1);
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Reserved.set(SP::G2);
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Reserved.set(SP::G3);
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Reserved.set(SP::G4);
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Reserved.set(SP::O6);
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Reserved.set(SP::I6);
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Reserved.set(SP::I7);
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Reserved.set(SP::G0);
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Reserved.set(SP::G5);
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Reserved.set(SP::G6);
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Reserved.set(SP::G7);
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return Reserved;
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}
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void SparcRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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MachineInstr &MI = *I;
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DebugLoc dl = MI.getDebugLoc();
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int Size = MI.getOperand(0).getImm();
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if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
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Size = -Size;
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if (Size)
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BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
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MBB.erase(I);
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}
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void
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SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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DebugLoc dl = MI.getDebugLoc();
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getIndex();
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// Addressable stack objects are accessed using neg. offsets from %fp
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MachineFunction &MF = *MI.getParent()->getParent();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(i+1).getImm();
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(i).ChangeToRegister(SP::I6, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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unsigned OffHi = (unsigned)Offset >> 10U;
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(SP::I6);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(i).ChangeToRegister(SP::G1, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
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}
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}
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unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return SP::I6;
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}
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unsigned SparcRegisterInfo::getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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}
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unsigned SparcRegisterInfo::getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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}
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