mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-30 17:33:24 +00:00
268e96a8a6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201479 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
3.6 KiB
LLVM
100 lines
3.6 KiB
LLVM
; RUN: llc -filetype=asm -o - < %s -mtriple arm-arm-none-eabi -disable-fp-elim| FileCheck %s --check-prefix=CHECK-ARM
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; RUN: llc -filetype=asm -o - < %s -mtriple arm-arm-none-eabi | FileCheck %s --check-prefix=CHECK-ARM-FP-ELIM
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define void @test1() {
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%tmp = alloca [ 64 x i32 ] , align 4
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ret void
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}
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!8, !9}
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!llvm.ident = !{!10}
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!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/large.c] [DW_LANG_C99]
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!1 = metadata !{metadata !"large.c", metadata !"/tmp"}
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!2 = metadata !{}
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!3 = metadata !{metadata !4}
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!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"test1", metadata !"test1", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @test1, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [test1]
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!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/tmp/large.c]
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!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
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!7 = metadata !{null}
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!8 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
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!9 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}
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!10 = metadata !{metadata !"clang version 3.5 "}
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!11 = metadata !{i32 2, i32 0, metadata !4, null}
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; CHECK-ARM-LABEL: test1:
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; CHECK-ARM: .cfi_startproc
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; CHECK-ARM: sub sp, sp, #256
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; CHECK-ARM: .cfi_endproc
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; CHECK-ARM-FP-ELIM-LABEL: test1:
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; CHECK-ARM-FP-ELIM: .cfi_startproc
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; CHECK-ARM-FP-ELIM: sub sp, sp, #256
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; CHECK-ARM-FP-ELIM: .cfi_endproc
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define void @test2() {
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%tmp = alloca [ 4168 x i8 ] , align 4
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ret void
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}
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; CHECK-ARM-LABEL: test2:
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; CHECK-ARM: .cfi_startproc
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; CHECK-ARM: push {r4, r5}
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; CHECK-ARM: .cfi_def_cfa_offset 8
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; CHECK-ARM: .cfi_offset r5, -4
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; CHECK-ARM: .cfi_offset r4, -8
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; CHECK-ARM: sub sp, sp, #72
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; CHECK-ARM: sub sp, sp, #4096
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; CHECK-ARM: .cfi_def_cfa_offset 4176
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; CHECK-ARM: .cfi_endproc
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; CHECK-ARM-FP_ELIM-LABEL: test2:
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; CHECK-ARM-FP_ELIM: .cfi_startproc
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; CHECK-ARM-FP_ELIM: push {r4, r5}
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; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 8
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; CHECK-ARM-FP_ELIM: .cfi_offset 54, -4
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; CHECK-ARM-FP_ELIM: .cfi_offset r4, -8
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; CHECK-ARM-FP_ELIM: sub sp, sp, #72
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; CHECK-ARM-FP_ELIM: sub sp, sp, #4096
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; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 4176
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; CHECK-ARM-FP_ELIM: .cfi_endproc
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define i32 @test3() {
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%retval = alloca i32, align 4
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%tmp = alloca i32, align 4
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%a = alloca [805306369 x i8], align 16
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store i32 0, i32* %tmp
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%tmp1 = load i32* %tmp
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ret i32 %tmp1
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}
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; CHECK-ARM-LABEL: test3:
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; CHECK-ARM: .cfi_startproc
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; CHECK-ARM: push {r4, r5, r11}
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; CHECK-ARM: .cfi_def_cfa_offset 12
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; CHECK-ARM: .cfi_offset r11, -4
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; CHECK-ARM: .cfi_offset r5, -8
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; CHECK-ARM: .cfi_offset r4, -12
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; CHECK-ARM: add r11, sp, #8
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; CHECK-ARM: .cfi_def_cfa r11, 4
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; CHECK-ARM: sub sp, sp, #20
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; CHECK-ARM: sub sp, sp, #805306368
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; CHECK-ARM: bic sp, sp, #15
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; CHECK-ARM: .cfi_endproc
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; CHECK-ARM-FP-ELIM-LABEL: test3:
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; CHECK-ARM-FP-ELIM: .cfi_startproc
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; CHECK-ARM-FP-ELIM: push {r4, r5, r11}
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; CHECK-ARM-FP-ELIM: .cfi_def_cfa_offset 12
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; CHECK-ARM-FP-ELIM: .cfi_offset r11, -4
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; CHECK-ARM-FP-ELIM: .cfi_offset r5, -8
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; CHECK-ARM-FP-ELIM: .cfi_offset r4, -12
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; CHECK-ARM-FP-ELIM: add r11, sp, #8
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; CHECK-ARM-FP-ELIM: .cfi_def_cfa r11, 4
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; CHECK-ARM-FP-ELIM: sub sp, sp, #20
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; CHECK-ARM-FP-ELIM: sub sp, sp, #805306368
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; CHECK-ARM-FP-ELIM: bic sp, sp, #15
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; CHECK-ARM-FP-ELIM: .cfi_endproc
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