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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
3.1 KiB
C++
82 lines
3.1 KiB
C++
//===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling on PowerPC processors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PPCHAZRECS_H
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#define PPCHAZRECS_H
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#include "llvm/CodeGen/ScheduleDAG.h"
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namespace llvm {
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/// PPCHazardRecognizer970 - This class defines a finite state automata that
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/// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
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/// promotes good dispatch group formation and implements noop insertion to
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/// avoid structural hazards that cause significant performance penalties (e.g.
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/// setting the CTR register then branching through it within a dispatch group),
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/// or storing then loading from the same address within a dispatch group.
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class PPCHazardRecognizer970 : public HazardRecognizer {
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unsigned NumIssued; // Number of insts issued, including advanced cycles.
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// Number of various types of instructions in the current dispatch group.
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unsigned NumFXU; // Number of Fixed Point (integer) instructions
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unsigned NumLSU; // Number of Load/Store instructions
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unsigned NumFPU; // Number of Floating Point instructions
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bool HasCR; // True if Condition Register instruction issued
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bool HasSPR; // True if Special-Purpose Register instruction used
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bool HasVALU; // True if Vector Arithmetic instruction issued
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bool HasVPERM; // True if Vector Permute instruction issued
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// Various things that can cause a structural hazard.
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// HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
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bool HasCTRSet;
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// StoredPtr - Keep track of the address of any store. If we see a load from
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// the same address (or one that aliases it), disallow the store. We only
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// need one pointer here, because there can only be two LSU operations and we
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// only get an LSU reject if the first is a store and the second is a load.
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//
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// This is null if we haven't seen a store yet. We keep track of both
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// operands of the store here, since we support [r+r] and [r+i] addressing.
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SDOperand StorePtr1, StorePtr2;
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unsigned StoreSize;
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public:
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PPCHazardRecognizer970();
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virtual HazardType getHazardType(SDNode *Node);
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virtual void EmitInstruction(SDNode *Node);
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virtual void AdvanceCycle();
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virtual void EmitNoop();
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private:
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/// EndDispatchGroup - Called when we are finishing a new dispatch group.
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///
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void EndDispatchGroup();
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enum PPC970InstrType {
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FXU, FXU_FIRST, LSU_LD, LSU_ST, FPU, CR, SPR, VALU, VPERM, BR, PseudoInst
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};
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/// GetInstrType - Classify the specified powerpc opcode according to its
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/// pipeline.
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PPC970InstrType GetInstrType(unsigned Opcode);
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bool isLoadOfStoredAddress(unsigned LoadSize,
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SDOperand Ptr1, SDOperand Ptr2) const;
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};
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} // end namespace llvm
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#endif
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