mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
2.9 KiB
LLVM
94 lines
2.9 KiB
LLVM
; RUN: llc < %s -march=ppc32 | \
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; RUN: grep eqv | count 3
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; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
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; RUN: grep andc | count 3
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; RUN: llc < %s -march=ppc32 | \
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; RUN: grep orc | count 2
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; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
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; RUN: grep nor | count 3
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; RUN: llc < %s -march=ppc32 | \
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; RUN: grep nand | count 1
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define i32 @EQV1(i32 %X, i32 %Y) nounwind {
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%A = xor i32 %X, %Y ; <i32> [#uses=1]
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%B = xor i32 %A, -1 ; <i32> [#uses=1]
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ret i32 %B
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}
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define i32 @EQV2(i32 %X, i32 %Y) nounwind {
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%A = xor i32 %X, -1 ; <i32> [#uses=1]
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%B = xor i32 %A, %Y ; <i32> [#uses=1]
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ret i32 %B
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}
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define i32 @EQV3(i32 %X, i32 %Y) nounwind {
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%A = xor i32 %X, -1 ; <i32> [#uses=1]
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%B = xor i32 %Y, %A ; <i32> [#uses=1]
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ret i32 %B
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}
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define i32 @ANDC1(i32 %X, i32 %Y) nounwind {
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%A = xor i32 %Y, -1 ; <i32> [#uses=1]
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%B = and i32 %X, %A ; <i32> [#uses=1]
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ret i32 %B
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}
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define i32 @ANDC2(i32 %X, i32 %Y) nounwind {
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%A = xor i32 %X, -1 ; <i32> [#uses=1]
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%B = and i32 %A, %Y ; <i32> [#uses=1]
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ret i32 %B
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}
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define i32 @ORC1(i32 %X, i32 %Y) nounwind {
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%A = xor i32 %Y, -1 ; <i32> [#uses=1]
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%B = or i32 %X, %A ; <i32> [#uses=1]
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ret i32 %B
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}
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define i32 @ORC2(i32 %X, i32 %Y) nounwind {
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%A = xor i32 %X, -1 ; <i32> [#uses=1]
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%B = or i32 %A, %Y ; <i32> [#uses=1]
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ret i32 %B
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}
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define i32 @NOR1(i32 %X) nounwind {
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%Y = xor i32 %X, -1 ; <i32> [#uses=1]
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ret i32 %Y
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}
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define i32 @NOR2(i32 %X, i32 %Y) nounwind {
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%Z = or i32 %X, %Y ; <i32> [#uses=1]
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%R = xor i32 %Z, -1 ; <i32> [#uses=1]
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ret i32 %R
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}
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define i32 @NAND1(i32 %X, i32 %Y) nounwind {
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%Z = and i32 %X, %Y ; <i32> [#uses=1]
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%W = xor i32 %Z, -1 ; <i32> [#uses=1]
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ret i32 %W
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}
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define void @VNOR(<4 x float>* %P, <4 x float>* %Q) nounwind {
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%tmp = load <4 x float>, <4 x float>* %P ; <<4 x float>> [#uses=1]
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%tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp2 = load <4 x float>, <4 x float>* %Q ; <<4 x float>> [#uses=1]
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%tmp2.upgrd.2 = bitcast <4 x float> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp3 = or <4 x i32> %tmp.upgrd.1, %tmp2.upgrd.2 ; <<4 x i32>> [#uses=1]
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%tmp4 = xor <4 x i32> %tmp3, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
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%tmp4.upgrd.3 = bitcast <4 x i32> %tmp4 to <4 x float> ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp4.upgrd.3, <4 x float>* %P
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ret void
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}
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define void @VANDC(<4 x float>* %P, <4 x float>* %Q) nounwind {
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%tmp = load <4 x float>, <4 x float>* %P ; <<4 x float>> [#uses=1]
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%tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp2 = load <4 x float>, <4 x float>* %Q ; <<4 x float>> [#uses=1]
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%tmp2.upgrd.5 = bitcast <4 x float> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp4 = xor <4 x i32> %tmp2.upgrd.5, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
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%tmp3 = and <4 x i32> %tmp.upgrd.4, %tmp4 ; <<4 x i32>> [#uses=1]
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%tmp4.upgrd.6 = bitcast <4 x i32> %tmp3 to <4 x float> ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp4.upgrd.6, <4 x float>* %P
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ret void
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}
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