mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
167 lines
3.8 KiB
LLVM
167 lines
3.8 KiB
LLVM
; Test 64-bit GPR accesses to a PC-relative location.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@gsrc16 = global i16 1
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@gsrc32 = global i32 1
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@gsrc64 = global i64 1
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@gdst16 = global i16 2
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@gdst32 = global i32 2
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@gdst64 = global i64 2
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@gsrc16u = global i16 1, align 1, section "foo"
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@gsrc32u = global i32 1, align 2, section "foo"
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@gsrc64u = global i64 1, align 4, section "foo"
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@gdst16u = global i16 2, align 1, section "foo"
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@gdst32u = global i32 2, align 2, section "foo"
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@gdst64u = global i64 2, align 4, section "foo"
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; Check sign-extending loads from i16.
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define i64 @f1() {
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; CHECK-LABEL: f1:
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; CHECK: lghrl %r2, gsrc16
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; CHECK: br %r14
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%val = load i16 , i16 *@gsrc16
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%ext = sext i16 %val to i64
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ret i64 %ext
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}
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; Check zero-extending loads from i16.
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define i64 @f2() {
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; CHECK-LABEL: f2:
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; CHECK: llghrl %r2, gsrc16
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; CHECK: br %r14
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%val = load i16 , i16 *@gsrc16
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%ext = zext i16 %val to i64
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ret i64 %ext
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}
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; Check sign-extending loads from i32.
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define i64 @f3() {
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; CHECK-LABEL: f3:
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; CHECK: lgfrl %r2, gsrc32
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; CHECK: br %r14
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%val = load i32 , i32 *@gsrc32
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%ext = sext i32 %val to i64
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ret i64 %ext
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}
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; Check zero-extending loads from i32.
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define i64 @f4() {
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; CHECK-LABEL: f4:
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; CHECK: llgfrl %r2, gsrc32
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; CHECK: br %r14
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%val = load i32 , i32 *@gsrc32
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%ext = zext i32 %val to i64
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ret i64 %ext
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}
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; Check truncating 16-bit stores.
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define void @f5(i64 %val) {
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; CHECK-LABEL: f5:
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; CHECK: sthrl %r2, gdst16
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; CHECK: br %r14
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%half = trunc i64 %val to i16
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store i16 %half, i16 *@gdst16
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ret void
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}
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; Check truncating 32-bit stores.
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define void @f6(i64 %val) {
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; CHECK-LABEL: f6:
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; CHECK: strl %r2, gdst32
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; CHECK: br %r14
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%word = trunc i64 %val to i32
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store i32 %word, i32 *@gdst32
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ret void
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}
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; Check plain loads and stores.
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define void @f7() {
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; CHECK-LABEL: f7:
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; CHECK: lgrl %r0, gsrc64
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; CHECK: stgrl %r0, gdst64
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; CHECK: br %r14
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%val = load i64 , i64 *@gsrc64
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store i64 %val, i64 *@gdst64
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ret void
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}
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; Repeat f1 with an unaligned variable.
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define i64 @f8() {
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; CHECK-LABEL: f8:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
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; CHECK: lgh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 , i16 *@gsrc16u, align 1
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%ext = sext i16 %val to i64
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ret i64 %ext
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}
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; Repeat f2 with an unaligned variable.
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define i64 @f9() {
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; CHECK-LABEL: f9:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
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; CHECK: llgh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 , i16 *@gsrc16u, align 1
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%ext = zext i16 %val to i64
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ret i64 %ext
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}
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; Repeat f3 with an unaligned variable.
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define i64 @f10() {
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; CHECK-LABEL: f10:
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; CHECK: larl [[REG:%r[0-5]]], gsrc32u
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; CHECK: lgf %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i32 , i32 *@gsrc32u, align 2
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%ext = sext i32 %val to i64
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ret i64 %ext
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}
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; Repeat f4 with an unaligned variable.
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define i64 @f11() {
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; CHECK-LABEL: f11:
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; CHECK: larl [[REG:%r[0-5]]], gsrc32u
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; CHECK: llgf %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i32 , i32 *@gsrc32u, align 2
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%ext = zext i32 %val to i64
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ret i64 %ext
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}
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; Repeat f5 with an unaligned variable.
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define void @f12(i64 %val) {
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; CHECK-LABEL: f12:
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; CHECK: lgrl [[REG:%r[0-5]]], gdst16u@GOT
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; CHECK: sth %r2, 0([[REG]])
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; CHECK: br %r14
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%half = trunc i64 %val to i16
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store i16 %half, i16 *@gdst16u, align 1
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ret void
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}
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; Repeat f6 with an unaligned variable.
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define void @f13(i64 %val) {
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; CHECK-LABEL: f13:
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; CHECK: larl [[REG:%r[0-5]]], gdst32u
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; CHECK: st %r2, 0([[REG]])
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; CHECK: br %r14
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%word = trunc i64 %val to i32
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store i32 %word, i32 *@gdst32u, align 2
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ret void
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}
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; Repeat f7 with unaligned variables.
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define void @f14() {
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; CHECK-LABEL: f14:
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; CHECK: larl [[REG:%r[0-5]]], gsrc64u
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; CHECK: lg [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: larl [[REG:%r[0-5]]], gdst64u
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; CHECK: stg [[VAL]], 0([[REG]])
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; CHECK: br %r14
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%val = load i64 , i64 *@gsrc64u, align 4
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store i64 %val, i64 *@gdst64u, align 4
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ret void
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}
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