mirror of
https://github.com/c64scene-ar/llvm-6502.git
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942827b113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
4.5 KiB
LLVM
129 lines
4.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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;; Scalar Integer Compare
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define i64 @test_vceqd(i64 %a, i64 %b) {
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; CHECK: test_vceqd
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; CHECK: cmeq {{d[0-9]+}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vceq.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vceq1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vceq2.i = call <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64> %vceq.i, <1 x i64> %vceq1.i)
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%0 = extractelement <1 x i64> %vceq2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vceqzd(i64 %a) {
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; CHECK: test_vceqzd
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; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vceqz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vceqz1.i = call <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64> %vceqz.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vceqz1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcged(i64 %a, i64 %b) {
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; CHECK: test_vcged
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcge.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcge1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
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%0 = extractelement <1 x i64> %vcge2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcgezd(i64 %a) {
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; CHECK: test_vcgezd
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcgez.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgez1.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcgez.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vcgez1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcgtd(i64 %a, i64 %b) {
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; CHECK: test_vcgtd
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcgt.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgt1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
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%0 = extractelement <1 x i64> %vcgt2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcgtzd(i64 %a) {
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; CHECK: test_vcgtzd
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcgtz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgtz1.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgtz.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vcgtz1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcled(i64 %a, i64 %b) {
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; CHECK: test_vcled
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcgt.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcgt1.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
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%0 = extractelement <1 x i64> %vcgt2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vclezd(i64 %a) {
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; CHECK: test_vclezd
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; CHECK: cmle {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vclez.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vclez1.i = call <1 x i64> @llvm.aarch64.neon.vclez(<1 x i64> %vclez.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vclez1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcltd(i64 %a, i64 %b) {
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; CHECK: test_vcltd
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcge.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcge1.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
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%0 = extractelement <1 x i64> %vcge2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcltzd(i64 %a) {
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; CHECK: test_vcltzd
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; CHECK: cmlt {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcltz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcltz1.i = call <1 x i64> @llvm.aarch64.neon.vcltz(<1 x i64> %vcltz.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vcltz1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vtstd(i64 %a, i64 %b) {
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; CHECK: test_vtstd
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; CHECK: cmtst {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vtst.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vtst1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vtst2.i = call <1 x i64> @llvm.aarch64.neon.vtstd(<1 x i64> %vtst.i, <1 x i64> %vtst1.i)
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%0 = extractelement <1 x i64> %vtst2.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vtstd(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.vcltz(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.vchs(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.vclez(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.vchi(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64>, <1 x i64>)
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