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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
375 lines
14 KiB
C++
375 lines
14 KiB
C++
//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass eliminates machine instruction PHI nodes by inserting copy
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// instructions. This destroys SSA information, but is the desired input for
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// some register allocators.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "phielim"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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#include <algorithm>
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#include <map>
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using namespace llvm;
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STATISTIC(NumAtomic, "Number of atomic phis lowered");
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namespace {
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class VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
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MachineRegisterInfo *MRI; // Machine register information
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public:
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static char ID; // Pass identification, replacement for typeid
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PNE() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
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/// in predecessor basic blocks.
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///
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bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
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void LowerAtomicPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator AfterPHIsIt);
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/// analyzePHINodes - Gather information about the PHI nodes in
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/// here. In particular, we want to map the number of uses of a virtual
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/// register which is used in a PHI node. We map that to the BB the
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/// vreg is coming from. This is used later to determine when the vreg
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/// is killed in the BB.
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///
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void analyzePHINodes(const MachineFunction& Fn);
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typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair;
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typedef std::map<BBVRegPair, unsigned> VRegPHIUse;
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VRegPHIUse VRegPHIUseCount;
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// Defs of PHI sources which are implicit_def.
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SmallPtrSet<MachineInstr*, 4> ImpDefs;
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};
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}
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char PNE::ID = 0;
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static RegisterPass<PNE>
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X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
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const PassInfo *const llvm::PHIEliminationID = &X;
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bool PNE::runOnMachineFunction(MachineFunction &Fn) {
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MRI = &Fn.getRegInfo();
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analyzePHINodes(Fn);
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bool Changed = false;
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// Eliminate PHI instructions by inserting copies into predecessor blocks.
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for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
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Changed |= EliminatePHINodes(Fn, *I);
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// Remove dead IMPLICIT_DEF instructions.
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for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(),
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E = ImpDefs.end(); I != E; ++I) {
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MachineInstr *DefMI = *I;
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unsigned DefReg = DefMI->getOperand(0).getReg();
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if (MRI->use_empty(DefReg))
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DefMI->eraseFromParent();
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}
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ImpDefs.clear();
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VRegPHIUseCount.clear();
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return Changed;
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}
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/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
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/// predecessor basic blocks.
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///
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bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
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if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
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return false; // Quick exit for basic blocks without PHIs.
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// Get an iterator to the first instruction after the last PHI node (this may
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// also be the end of the basic block).
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MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
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while (AfterPHIsIt != MBB.end() &&
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AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI)
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++AfterPHIsIt; // Skip over all of the PHI nodes...
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while (MBB.front().getOpcode() == TargetInstrInfo::PHI)
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LowerAtomicPHINode(MBB, AfterPHIsIt);
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return true;
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}
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/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
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/// are implicit_def's.
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static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
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const MachineRegisterInfo *MRI) {
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
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unsigned SrcReg = MPhi->getOperand(i).getReg();
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const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
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if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
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return false;
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}
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return true;
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}
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/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
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/// under the assuption that it needs to be lowered in a way that supports
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/// atomic execution of PHIs. This lowering method is always correct all of the
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/// time.
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///
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void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator AfterPHIsIt) {
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// Unlink the PHI node from the basic block, but don't delete the PHI yet.
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MachineInstr *MPhi = MBB.remove(MBB.begin());
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unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
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unsigned DestReg = MPhi->getOperand(0).getReg();
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bool isDead = MPhi->getOperand(0).isDead();
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// Create a new register for the incoming PHI arguments.
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MachineFunction &MF = *MBB.getParent();
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const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
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unsigned IncomingReg = 0;
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// Insert a register to register copy at the top of the current block (but
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// after any remaining phi nodes) which copies the new incoming register
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// into the phi node destination.
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const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
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if (isSourceDefinedByImplicitDef(MPhi, MRI))
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// If all sources of a PHI node are implicit_def, just emit an
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// implicit_def instead of a copy.
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BuildMI(MBB, AfterPHIsIt,
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TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
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else {
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IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
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}
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// Update live variable information if there is any.
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LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
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if (LV) {
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MachineInstr *PHICopy = prior(AfterPHIsIt);
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if (IncomingReg) {
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// Increment use count of the newly created virtual register.
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LV->getVarInfo(IncomingReg).NumUses++;
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// Add information to LiveVariables to know that the incoming value is
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// killed. Note that because the value is defined in several places (once
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// each for each incoming block), the "def" block and instruction fields
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// for the VarInfo is not filled in.
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LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
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LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
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}
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// Since we are going to be deleting the PHI node, if it is the last use of
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// any registers, or if the value itself is dead, we need to move this
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// information over to the new copy we just inserted.
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LV->removeVirtualRegistersKilled(MPhi);
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// If the result is dead, update LV.
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if (isDead) {
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LV->addVirtualRegisterDead(DestReg, PHICopy);
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LV->removeVirtualRegisterDead(DestReg, MPhi);
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}
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}
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// Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
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for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
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--VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
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MPhi->getOperand(i).getReg())];
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// Now loop over all of the incoming arguments, changing them to copy into the
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// IncomingReg register in the corresponding predecessor basic block.
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SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
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for (int i = NumSrcs - 1; i >= 0; --i) {
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unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
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assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
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"Machine PHI Operands must all be virtual registers!");
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// If source is defined by an implicit def, there is no need to insert a
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// copy.
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MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
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if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
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ImpDefs.insert(DefMI);
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continue;
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}
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// Get the MachineBasicBlock equivalent of the BasicBlock that is the source
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// path the PHI.
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MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
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// Check to make sure we haven't already emitted the copy for this block.
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// This can happen because PHI nodes may have multiple entries for the same
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// basic block.
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if (!MBBsInsertedInto.insert(&opBlock))
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continue; // If the copy has already been emitted, we're done.
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// Find a safe location to insert the copy, this may be the first terminator
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// in the block (or end()).
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MachineBasicBlock::iterator InsertPos = opBlock.getFirstTerminator();
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// Insert the copy.
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TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
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// Now update live variable information if we have it. Otherwise we're done
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if (!LV) continue;
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// We want to be able to insert a kill of the register if this PHI (aka, the
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// copy we just inserted) is the last use of the source value. Live
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// variable analysis conservatively handles this by saying that the value is
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// live until the end of the block the PHI entry lives in. If the value
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// really is dead at the PHI copy, there will be no successor blocks which
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// have the value live-in.
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//
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// Check to see if the copy is the last use, and if so, update the live
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// variables information so that it knows the copy source instruction kills
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// the incoming value.
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LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg);
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InRegVI.UsedBlocks[opBlock.getNumber()] = true;
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// Loop over all of the successors of the basic block, checking to see if
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// the value is either live in the block, or if it is killed in the block.
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// Also check to see if this register is in use by another PHI node which
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// has not yet been eliminated. If so, it will be killed at an appropriate
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// point later.
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// Is it used by any PHI instructions in this block?
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bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
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std::vector<MachineBasicBlock*> OpSuccBlocks;
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// Otherwise, scan successors, including the BB the PHI node lives in.
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for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
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E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) {
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MachineBasicBlock *SuccMBB = *SI;
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// Is it alive in this successor?
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unsigned SuccIdx = SuccMBB->getNumber();
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if (SuccIdx < InRegVI.AliveBlocks.size() &&
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InRegVI.AliveBlocks[SuccIdx]) {
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ValueIsLive = true;
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break;
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}
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OpSuccBlocks.push_back(SuccMBB);
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}
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// Check to see if this value is live because there is a use in a successor
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// that kills it.
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if (!ValueIsLive) {
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switch (OpSuccBlocks.size()) {
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case 1: {
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MachineBasicBlock *MBB = OpSuccBlocks[0];
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for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
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if (InRegVI.Kills[i]->getParent() == MBB) {
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ValueIsLive = true;
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break;
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}
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break;
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}
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case 2: {
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MachineBasicBlock *MBB1 = OpSuccBlocks[0], *MBB2 = OpSuccBlocks[1];
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for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
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if (InRegVI.Kills[i]->getParent() == MBB1 ||
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InRegVI.Kills[i]->getParent() == MBB2) {
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ValueIsLive = true;
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break;
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}
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break;
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}
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default:
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std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
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for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
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if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
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InRegVI.Kills[i]->getParent())) {
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ValueIsLive = true;
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break;
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}
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}
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}
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// Okay, if we now know that the value is not live out of the block, we can
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// add a kill marker in this block saying that it kills the incoming value!
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if (!ValueIsLive) {
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// In our final twist, we have to decide which instruction kills the
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// register. In most cases this is the copy, however, the first
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// terminator instruction at the end of the block may also use the value.
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// In this case, we should mark *it* as being the killing block, not the
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// copy.
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MachineBasicBlock::iterator KillInst = prior(InsertPos);
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MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
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if (Term != opBlock.end()) {
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if (Term->readsRegister(SrcReg))
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KillInst = Term;
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// Check that no other terminators use values.
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#ifndef NDEBUG
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for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end();
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++TI) {
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assert(!TI->readsRegister(SrcReg) &&
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"Terminator instructions cannot use virtual registers unless"
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"they are the first terminator in a block!");
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}
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#endif
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}
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// Finally, mark it killed.
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LV->addVirtualRegisterKilled(SrcReg, KillInst);
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// This vreg no longer lives all of the way through opBlock.
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unsigned opBlockNum = opBlock.getNumber();
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if (opBlockNum < InRegVI.AliveBlocks.size())
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InRegVI.AliveBlocks[opBlockNum] = false;
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}
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}
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// Really delete the PHI instruction now!
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MF.DeleteMachineInstr(MPhi);
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++NumAtomic;
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}
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/// analyzePHINodes - Gather information about the PHI nodes in here. In
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/// particular, we want to map the number of uses of a virtual register which is
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/// used in a PHI node. We map that to the BB the vreg is coming from. This is
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/// used later to determine when the vreg is killed in the BB.
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///
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void PNE::analyzePHINodes(const MachineFunction& Fn) {
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for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
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I != E; ++I)
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for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
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BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
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for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
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++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
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BBI->getOperand(i).getReg())];
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}
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