Bill Wendling 7d9f2b93a3 This test case: ... long test(long x) { return (x & 123124) | 3; } Currently compiles to: _test: orl $3, %edi movq %rdi, %rax andq $123127, %rax ret This is because instruction and DAG combiners canonicalize (or (and x, C), D) -> (and (or, D), (C | D)) However, this is only profitable if (C & D) != 0. It gets in the way of the 3-addressification because the input bits are known to be zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97616 91177308-0d34-0410-b5e6-96231b3b80d8		2010-03-03 00:35:56 +00:00
..
Alpha	Fix PR2590 by making PatternSortingPredicate actually be	2010-03-01 22:09:11 +00:00
ARM	Check for comparisons of +/- zero when optimizing less-than-or-equal and	2010-02-24 22:15:53 +00:00
Blackfin	Change the scheduler from adding nodes in allnodes order	2010-02-24 06:11:37 +00:00
CBackend
CellSPU	don't let asm-verbose break the check-next lines in these tests.	2010-01-19 06:39:54 +00:00
CPP
Generic	stop using anders-aa	2010-03-01 20:24:05 +00:00
MBlaze	Adding the MicroBlaze backend.	2010-02-23 19:15:24 +00:00
Mips
MSP430	Fix some issues in WalkChainUsers dealing with	2010-03-02 22:20:06 +00:00
PIC16	this testcase is failing because pic16 doesn't define a reg/reg	2010-03-02 20:48:24 +00:00
PowerPC	add some random nounwinds.	2010-02-28 20:36:49 +00:00
SPARC	add support for the sparcv9-*-* target triple to turn on	2010-02-04 06:34:01 +00:00
SystemZ
Thumb	Run the pre-register allocation tail duplication pass by default. Remove	2010-01-16 00:29:50 +00:00
Thumb2	Create a stack frame on ARM when	2010-02-24 22:43:17 +00:00
X86	This test case:	2010-03-03 00:35:56 +00:00
XCore	Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.	2010-02-26 16:44:51 +00:00