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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
1.5 KiB
LLVM
51 lines
1.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; Test that we correctly commute a sub instruction
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; FUNC-LABEL: {{^}}sub_rev:
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; SI-NOT: v_sub_i32_e32 v{{[0-9]+}}, s
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; SI: v_subrev_i32_e32 v{{[0-9]+}}, s
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; ModuleID = 'vop-shrink.ll'
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define void @sub_rev(i32 addrspace(1)* %out, <4 x i32> %sgpr, i32 %cond) {
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entry:
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%vgpr = call i32 @llvm.r600.read.tidig.x() #1
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%tmp = icmp eq i32 %cond, 0
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br i1 %tmp, label %if, label %else
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if: ; preds = %entry
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%tmp1 = getelementptr i32 addrspace(1)* %out, i32 1
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%tmp2 = extractelement <4 x i32> %sgpr, i32 1
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store i32 %tmp2, i32 addrspace(1)* %out
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br label %endif
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else: ; preds = %entry
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%tmp3 = extractelement <4 x i32> %sgpr, i32 2
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%tmp4 = sub i32 %vgpr, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %out
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br label %endif
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endif: ; preds = %else, %if
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ret void
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}
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; Test that we fold an immediate that was illegal for a 64-bit op into the
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; 32-bit op when we shrink it.
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; FUNC-LABEL: {{^}}add_fold:
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; SI: v_add_f32_e32 v{{[0-9]+}}, 0x44800000
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define void @add_fold(float addrspace(1)* %out) {
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entry:
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%tmp = call i32 @llvm.r600.read.tidig.x()
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%tmp1 = uitofp i32 %tmp to float
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%tmp2 = fadd float %tmp1, 1.024000e+03
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store float %tmp2, float addrspace(1)* %out
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tidig.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { readnone }
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