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1991e2a4df
Summary: This instruction encodes a loading operation that may fault, and a label to branch to if the load page-faults. The locations of potentially faulting loads and their "handler" destinations are recorded in a FaultMap section, meant to be consumed by LLVM's clients. Nothing generates FAULTING_LOAD_OP instructions yet, but they will be used in a future change. The documentation (FaultMaps.rst) needs improvement and I will update this diff with a more expanded version shortly. Depends on D10196 Reviewers: rnk, reames, AndyAyers, ab, atrick, pgavlin Reviewed By: atrick, pgavlin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10197 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239740 91177308-0d34-0410-b5e6-96231b3b80d8
1206 lines
48 KiB
TableGen
1206 lines
48 KiB
TableGen
//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent interfaces which should be
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// implemented by each target which is using a TableGen based code generator.
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//
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//===----------------------------------------------------------------------===//
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// Include all information about LLVM intrinsics.
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include "llvm/IR/Intrinsics.td"
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//===----------------------------------------------------------------------===//
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// Register file description - These classes are used to fill in the target
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// description classes.
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class RegisterClass; // Forward def
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// SubRegIndex - Use instances of SubRegIndex to identify subregisters.
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class SubRegIndex<int size, int offset = 0> {
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string Namespace = "";
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// Size - Size (in bits) of the sub-registers represented by this index.
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int Size = size;
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// Offset - Offset of the first bit that is part of this sub-register index.
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// Set it to -1 if the same index is used to represent sub-registers that can
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// be at different offsets (for example when using an index to access an
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// element in a register tuple).
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int Offset = offset;
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// ComposedOf - A list of two SubRegIndex instances, [A, B].
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// This indicates that this SubRegIndex is the result of composing A and B.
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// See ComposedSubRegIndex.
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list<SubRegIndex> ComposedOf = [];
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// CoveringSubRegIndices - A list of two or more sub-register indexes that
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// cover this sub-register.
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//
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// This field should normally be left blank as TableGen can infer it.
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//
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// TableGen automatically detects sub-registers that straddle the registers
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// in the SubRegs field of a Register definition. For example:
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//
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// Q0 = dsub_0 -> D0, dsub_1 -> D1
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// Q1 = dsub_0 -> D2, dsub_1 -> D3
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// D1_D2 = dsub_0 -> D1, dsub_1 -> D2
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// QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
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//
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// TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
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// the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
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// CoveringSubRegIndices = [dsub_1, dsub_2].
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list<SubRegIndex> CoveringSubRegIndices = [];
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}
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// ComposedSubRegIndex - A sub-register that is the result of composing A and B.
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// Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
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class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
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: SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
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!if(!eq(B.Offset, -1), -1,
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!add(A.Offset, B.Offset)))> {
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// See SubRegIndex.
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let ComposedOf = [A, B];
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}
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// RegAltNameIndex - The alternate name set to use for register operands of
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// this register class when printing.
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class RegAltNameIndex {
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string Namespace = "";
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}
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def NoRegAltName : RegAltNameIndex;
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// Register - You should define one instance of this class for each register
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// in the target machine. String n will become the "name" of the register.
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class Register<string n, list<string> altNames = []> {
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string Namespace = "";
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string AsmName = n;
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list<string> AltNames = altNames;
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// Aliases - A list of registers that this register overlaps with. A read or
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// modification of this register can potentially read or modify the aliased
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// registers.
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list<Register> Aliases = [];
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// SubRegs - A list of registers that are parts of this register. Note these
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// are "immediate" sub-registers and the registers within the list do not
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// themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
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// not [AX, AH, AL].
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list<Register> SubRegs = [];
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// SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
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// to address it. Sub-sub-register indices are automatically inherited from
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// SubRegs.
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list<SubRegIndex> SubRegIndices = [];
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// RegAltNameIndices - The alternate name indices which are valid for this
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// register.
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list<RegAltNameIndex> RegAltNameIndices = [];
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// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
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// These values can be determined by locating the <target>.h file in the
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// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
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// order of these names correspond to the enumeration used by gcc. A value of
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// -1 indicates that the gcc number is undefined and -2 that register number
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// is invalid for this mode/flavour.
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list<int> DwarfNumbers = [];
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// CostPerUse - Additional cost of instructions using this register compared
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// to other registers in its class. The register allocator will try to
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// minimize the number of instructions using a register with a CostPerUse.
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// This is used by the x86-64 and ARM Thumb targets where some registers
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// require larger instruction encodings.
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int CostPerUse = 0;
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// CoveredBySubRegs - When this bit is set, the value of this register is
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// completely determined by the value of its sub-registers. For example, the
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// x86 register AX is covered by its sub-registers AL and AH, but EAX is not
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// covered by its sub-register AX.
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bit CoveredBySubRegs = 0;
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// HWEncoding - The target specific hardware encoding for this register.
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bits<16> HWEncoding = 0;
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}
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// RegisterWithSubRegs - This can be used to define instances of Register which
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// need to specify sub-registers.
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// List "subregs" specifies which registers are sub-registers to this one. This
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// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
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// This allows the code generator to be careful not to put two values with
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// overlapping live ranges into registers which alias.
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class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
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let SubRegs = subregs;
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}
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// DAGOperand - An empty base class that unifies RegisterClass's and other forms
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// of Operand's that are legal as type qualifiers in DAG patterns. This should
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// only ever be used for defining multiclasses that are polymorphic over both
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// RegisterClass's and other Operand's.
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class DAGOperand { }
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// RegisterClass - Now that all of the registers are defined, and aliases
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// between registers are defined, specify which registers belong to which
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// register classes. This also defines the default allocation order of
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// registers by register allocators.
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//
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class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
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dag regList, RegAltNameIndex idx = NoRegAltName>
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: DAGOperand {
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string Namespace = namespace;
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// RegType - Specify the list ValueType of the registers in this register
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// class. Note that all registers in a register class must have the same
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// ValueTypes. This is a list because some targets permit storing different
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// types in same register, for example vector values with 128-bit total size,
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// but different count/size of items, like SSE on x86.
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//
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list<ValueType> RegTypes = regTypes;
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// Size - Specify the spill size in bits of the registers. A default value of
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// zero lets tablgen pick an appropriate size.
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int Size = 0;
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// Alignment - Specify the alignment required of the registers when they are
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// stored or loaded to memory.
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//
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int Alignment = alignment;
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// CopyCost - This value is used to specify the cost of copying a value
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// between two registers in this register class. The default value is one
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// meaning it takes a single instruction to perform the copying. A negative
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// value means copying is extremely expensive or impossible.
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int CopyCost = 1;
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// MemberList - Specify which registers are in this class. If the
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// allocation_order_* method are not specified, this also defines the order of
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// allocation used by the register allocator.
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//
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dag MemberList = regList;
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// AltNameIndex - The alternate register name to use when printing operands
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// of this register class. Every register in the register class must have
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// a valid alternate name for the given index.
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RegAltNameIndex altNameIndex = idx;
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// isAllocatable - Specify that the register class can be used for virtual
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// registers and register allocation. Some register classes are only used to
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// model instruction operand constraints, and should have isAllocatable = 0.
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bit isAllocatable = 1;
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// AltOrders - List of alternative allocation orders. The default order is
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// MemberList itself, and that is good enough for most targets since the
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// register allocators automatically remove reserved registers and move
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// callee-saved registers to the end.
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list<dag> AltOrders = [];
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// AltOrderSelect - The body of a function that selects the allocation order
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// to use in a given machine function. The code will be inserted in a
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// function like this:
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//
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// static inline unsigned f(const MachineFunction &MF) { ... }
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//
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// The function should return 0 to select the default order defined by
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// MemberList, 1 to select the first AltOrders entry and so on.
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code AltOrderSelect = [{}];
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// Specify allocation priority for register allocators using a greedy
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// heuristic. Classes with higher priority values are assigned first. This is
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// useful as it is sometimes beneficial to assign registers to highly
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// constrained classes first. The value has to be in the range [0,63].
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int AllocationPriority = 0;
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}
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// The memberList in a RegisterClass is a dag of set operations. TableGen
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// evaluates these set operations and expand them into register lists. These
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// are the most common operation, see test/TableGen/SetTheory.td for more
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// examples of what is possible:
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//
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// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
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// register class, or a sub-expression. This is also the way to simply list
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// registers.
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//
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// (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
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//
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// (and GPR, CSR) - Set intersection. All registers from the first set that are
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// also in the second set.
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//
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// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
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// numbered registers. Takes an optional 4th operand which is a stride to use
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// when generating the sequence.
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//
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// (shl GPR, 4) - Remove the first N elements.
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//
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// (trunc GPR, 4) - Truncate after the first N elements.
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//
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// (rotl GPR, 1) - Rotate N places to the left.
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//
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// (rotr GPR, 1) - Rotate N places to the right.
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//
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// (decimate GPR, 2) - Pick every N'th element, starting with the first.
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//
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// (interleave A, B, ...) - Interleave the elements from each argument list.
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//
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// All of these operators work on ordered sets, not lists. That means
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// duplicates are removed from sub-expressions.
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// Set operators. The rest is defined in TargetSelectionDAG.td.
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def sequence;
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def decimate;
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def interleave;
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// RegisterTuples - Automatically generate super-registers by forming tuples of
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// sub-registers. This is useful for modeling register sequence constraints
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// with pseudo-registers that are larger than the architectural registers.
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//
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// The sub-register lists are zipped together:
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//
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// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
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//
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// Generates the same registers as:
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//
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// let SubRegIndices = [sube, subo] in {
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// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
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// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
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// }
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//
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// The generated pseudo-registers inherit super-classes and fields from their
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// first sub-register. Most fields from the Register class are inferred, and
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// the AsmName and Dwarf numbers are cleared.
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//
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// RegisterTuples instances can be used in other set operations to form
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// register classes and so on. This is the only way of using the generated
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// registers.
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class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
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// SubRegs - N lists of registers to be zipped up. Super-registers are
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// synthesized from the first element of each SubRegs list, the second
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// element and so on.
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list<dag> SubRegs = Regs;
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// SubRegIndices - N SubRegIndex instances. This provides the names of the
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// sub-registers in the synthesized super-registers.
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list<SubRegIndex> SubRegIndices = Indices;
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}
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//===----------------------------------------------------------------------===//
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// DwarfRegNum - This class provides a mapping of the llvm register enumeration
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// to the register numbering used by gcc and gdb. These values are used by a
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// debug information writer to describe where values may be located during
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// execution.
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class DwarfRegNum<list<int> Numbers> {
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// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
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// These values can be determined by locating the <target>.h file in the
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// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
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// order of these names correspond to the enumeration used by gcc. A value of
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// -1 indicates that the gcc number is undefined and -2 that register number
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// is invalid for this mode/flavour.
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list<int> DwarfNumbers = Numbers;
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}
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// DwarfRegAlias - This class declares that a given register uses the same dwarf
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// numbers as another one. This is useful for making it clear that the two
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// registers do have the same number. It also lets us build a mapping
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// from dwarf register number to llvm register.
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class DwarfRegAlias<Register reg> {
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Register DwarfAlias = reg;
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}
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//===----------------------------------------------------------------------===//
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// Pull in the common support for scheduling
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//
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include "llvm/Target/TargetSchedule.td"
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class Predicate; // Forward def
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//===----------------------------------------------------------------------===//
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// Instruction set description - These classes correspond to the C++ classes in
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// the Target/TargetInstrInfo.h file.
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//
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class Instruction {
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string Namespace = "";
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dag OutOperandList; // An dag containing the MI def operand list.
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dag InOperandList; // An dag containing the MI use operand list.
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string AsmString = ""; // The .s format to print the instruction with.
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// Pattern - Set to the DAG pattern for this instruction, if we know of one,
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// otherwise, uninitialized.
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list<dag> Pattern;
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// The follow state will eventually be inferred automatically from the
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// instruction pattern.
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list<Register> Uses = []; // Default to using no non-operand registers
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list<Register> Defs = []; // Default to modifying no non-operand registers
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// Predicates - List of predicates which will be turned into isel matching
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// code.
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list<Predicate> Predicates = [];
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// Size - Size of encoded instruction, or zero if the size cannot be determined
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// from the opcode.
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int Size = 0;
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// DecoderNamespace - The "namespace" in which this instruction exists, on
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// targets like ARM which multiple ISA namespaces exist.
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string DecoderNamespace = "";
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// Code size, for instruction selection.
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// FIXME: What does this actually mean?
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int CodeSize = 0;
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// Added complexity passed onto matching pattern.
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int AddedComplexity = 0;
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// These bits capture information about the high-level semantics of the
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// instruction.
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bit isReturn = 0; // Is this instruction a return instruction?
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bit isBranch = 0; // Is this instruction a branch instruction?
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bit isIndirectBranch = 0; // Is this instruction an indirect branch?
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bit isCompare = 0; // Is this instruction a comparison instruction?
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bit isMoveImm = 0; // Is this instruction a move immediate instruction?
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bit isBitcast = 0; // Is this instruction a bitcast instruction?
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bit isSelect = 0; // Is this instruction a select instruction?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
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bit mayLoad = ?; // Is it possible for this inst to read memory?
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bit mayStore = ?; // Is it possible for this inst to write memory?
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bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
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bit isCommutable = 0; // Is this 3 operand instruction commutable?
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bit isTerminator = 0; // Is this part of the terminator for a basic block?
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bit isReMaterializable = 0; // Is this instruction re-materializable?
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bit isPredicable = 0; // Is this instruction predicable?
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bit hasDelaySlot = 0; // Does this instruction have an delay slot?
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bit usesCustomInserter = 0; // Pseudo instr needing special help.
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bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
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bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
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bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
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bit isConvergent = 0; // Is this instruction convergent?
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bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
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bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
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bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
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bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
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// If so, make sure to override
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// TargetInstrInfo::getRegSequenceLikeInputs.
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bit isPseudo = 0; // Is this instruction a pseudo-instruction?
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// If so, won't have encoding information for
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// the [MC]CodeEmitter stuff.
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bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
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// If so, make sure to override
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// TargetInstrInfo::getExtractSubregLikeInputs.
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bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
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// If so, make sure to override
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// TargetInstrInfo::getInsertSubregLikeInputs.
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// Side effect flags - When set, the flags have these meanings:
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//
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// hasSideEffects - The instruction has side effects that are not
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// captured by any operands of the instruction or other flags.
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//
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bit hasSideEffects = ?;
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// Is this instruction a "real" instruction (with a distinct machine
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// encoding), or is it a pseudo instruction used for codegen modeling
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// purposes.
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// FIXME: For now this is distinct from isPseudo, above, as code-gen-only
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// instructions can (and often do) still have encoding information
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// associated with them. Once we've migrated all of them over to true
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// pseudo-instructions that are lowered to real instructions prior to
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// the printer/emitter, we can remove this attribute and just use isPseudo.
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//
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// The intended use is:
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// isPseudo: Does not have encoding information and should be expanded,
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// at the latest, during lowering to MCInst.
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//
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// isCodeGenOnly: Does have encoding information and can go through to the
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// CodeEmitter unchanged, but duplicates a canonical instruction
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// definition's encoding and should be ignored when constructing the
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// assembler match tables.
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bit isCodeGenOnly = 0;
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// Is this instruction a pseudo instruction for use by the assembler parser.
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bit isAsmParserOnly = 0;
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InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
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// Scheduling information from TargetSchedule.td.
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list<SchedReadWrite> SchedRW;
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string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
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/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
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/// be encoded into the output machineinstr.
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string DisableEncoding = "";
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string PostEncoderMethod = "";
|
|
string DecoderMethod = "";
|
|
|
|
/// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
|
|
bits<64> TSFlags = 0;
|
|
|
|
///@name Assembler Parser Support
|
|
///@{
|
|
|
|
string AsmMatchConverter = "";
|
|
|
|
/// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
|
|
/// two-operand matcher inst-alias for a three operand instruction.
|
|
/// For example, the arm instruction "add r3, r3, r5" can be written
|
|
/// as "add r3, r5". The constraint is of the same form as a tied-operand
|
|
/// constraint. For example, "$Rn = $Rd".
|
|
string TwoOperandAliasConstraint = "";
|
|
|
|
///@}
|
|
|
|
/// UseNamedOperandTable - If set, the operand indices of this instruction
|
|
/// can be queried via the getNamedOperandIdx() function which is generated
|
|
/// by TableGen.
|
|
bit UseNamedOperandTable = 0;
|
|
}
|
|
|
|
/// PseudoInstExpansion - Expansion information for a pseudo-instruction.
|
|
/// Which instruction it expands to and how the operands map from the
|
|
/// pseudo.
|
|
class PseudoInstExpansion<dag Result> {
|
|
dag ResultInst = Result; // The instruction to generate.
|
|
bit isPseudo = 1;
|
|
}
|
|
|
|
/// Predicates - These are extra conditionals which are turned into instruction
|
|
/// selector matching code. Currently each predicate is just a string.
|
|
class Predicate<string cond> {
|
|
string CondString = cond;
|
|
|
|
/// AssemblerMatcherPredicate - If this feature can be used by the assembler
|
|
/// matcher, this is true. Targets should set this by inheriting their
|
|
/// feature from the AssemblerPredicate class in addition to Predicate.
|
|
bit AssemblerMatcherPredicate = 0;
|
|
|
|
/// AssemblerCondString - Name of the subtarget feature being tested used
|
|
/// as alternative condition string used for assembler matcher.
|
|
/// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
|
|
/// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
|
|
/// It can also list multiple features separated by ",".
|
|
/// e.g. "ModeThumb,FeatureThumb2" is translated to
|
|
/// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
|
|
string AssemblerCondString = "";
|
|
|
|
/// PredicateName - User-level name to use for the predicate. Mainly for use
|
|
/// in diagnostics such as missing feature errors in the asm matcher.
|
|
string PredicateName = "";
|
|
}
|
|
|
|
/// NoHonorSignDependentRounding - This predicate is true if support for
|
|
/// sign-dependent-rounding is not enabled.
|
|
def NoHonorSignDependentRounding
|
|
: Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
|
|
|
|
class Requires<list<Predicate> preds> {
|
|
list<Predicate> Predicates = preds;
|
|
}
|
|
|
|
/// ops definition - This is just a simple marker used to identify the operand
|
|
/// list for an instruction. outs and ins are identical both syntactically and
|
|
/// semantically; they are used to define def operands and use operands to
|
|
/// improve readibility. This should be used like this:
|
|
/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
|
|
def ops;
|
|
def outs;
|
|
def ins;
|
|
|
|
/// variable_ops definition - Mark this instruction as taking a variable number
|
|
/// of operands.
|
|
def variable_ops;
|
|
|
|
|
|
/// PointerLikeRegClass - Values that are designed to have pointer width are
|
|
/// derived from this. TableGen treats the register class as having a symbolic
|
|
/// type that it doesn't know, and resolves the actual regclass to use by using
|
|
/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
|
|
class PointerLikeRegClass<int Kind> {
|
|
int RegClassKind = Kind;
|
|
}
|
|
|
|
|
|
/// ptr_rc definition - Mark this operand as being a pointer value whose
|
|
/// register class is resolved dynamically via a callback to TargetInstrInfo.
|
|
/// FIXME: We should probably change this to a class which contain a list of
|
|
/// flags. But currently we have but one flag.
|
|
def ptr_rc : PointerLikeRegClass<0>;
|
|
|
|
/// unknown definition - Mark this operand as being of unknown type, causing
|
|
/// it to be resolved by inference in the context it is used.
|
|
class unknown_class;
|
|
def unknown : unknown_class;
|
|
|
|
/// AsmOperandClass - Representation for the kinds of operands which the target
|
|
/// specific parser can create and the assembly matcher may need to distinguish.
|
|
///
|
|
/// Operand classes are used to define the order in which instructions are
|
|
/// matched, to ensure that the instruction which gets matched for any
|
|
/// particular list of operands is deterministic.
|
|
///
|
|
/// The target specific parser must be able to classify a parsed operand into a
|
|
/// unique class which does not partially overlap with any other classes. It can
|
|
/// match a subset of some other class, in which case the super class field
|
|
/// should be defined.
|
|
class AsmOperandClass {
|
|
/// The name to use for this class, which should be usable as an enum value.
|
|
string Name = ?;
|
|
|
|
/// The super classes of this operand.
|
|
list<AsmOperandClass> SuperClasses = [];
|
|
|
|
/// The name of the method on the target specific operand to call to test
|
|
/// whether the operand is an instance of this class. If not set, this will
|
|
/// default to "isFoo", where Foo is the AsmOperandClass name. The method
|
|
/// signature should be:
|
|
/// bool isFoo() const;
|
|
string PredicateMethod = ?;
|
|
|
|
/// The name of the method on the target specific operand to call to add the
|
|
/// target specific operand to an MCInst. If not set, this will default to
|
|
/// "addFooOperands", where Foo is the AsmOperandClass name. The method
|
|
/// signature should be:
|
|
/// void addFooOperands(MCInst &Inst, unsigned N) const;
|
|
string RenderMethod = ?;
|
|
|
|
/// The name of the method on the target specific operand to call to custom
|
|
/// handle the operand parsing. This is useful when the operands do not relate
|
|
/// to immediates or registers and are very instruction specific (as flags to
|
|
/// set in a processor register, coprocessor number, ...).
|
|
string ParserMethod = ?;
|
|
|
|
// The diagnostic type to present when referencing this operand in a
|
|
// match failure error message. By default, use a generic "invalid operand"
|
|
// diagnostic. The target AsmParser maps these codes to text.
|
|
string DiagnosticType = "";
|
|
}
|
|
|
|
def ImmAsmOperand : AsmOperandClass {
|
|
let Name = "Imm";
|
|
}
|
|
|
|
/// Operand Types - These provide the built-in operand types that may be used
|
|
/// by a target. Targets can optionally provide their own operand types as
|
|
/// needed, though this should not be needed for RISC targets.
|
|
class Operand<ValueType ty> : DAGOperand {
|
|
ValueType Type = ty;
|
|
string PrintMethod = "printOperand";
|
|
string EncoderMethod = "";
|
|
string DecoderMethod = "";
|
|
string OperandType = "OPERAND_UNKNOWN";
|
|
dag MIOperandInfo = (ops);
|
|
|
|
// MCOperandPredicate - Optionally, a code fragment operating on
|
|
// const MCOperand &MCOp, and returning a bool, to indicate if
|
|
// the value of MCOp is valid for the specific subclass of Operand
|
|
code MCOperandPredicate;
|
|
|
|
// ParserMatchClass - The "match class" that operands of this type fit
|
|
// in. Match classes are used to define the order in which instructions are
|
|
// match, to ensure that which instructions gets matched is deterministic.
|
|
//
|
|
// The target specific parser must be able to classify an parsed operand into
|
|
// a unique class, which does not partially overlap with any other classes. It
|
|
// can match a subset of some other class, in which case the AsmOperandClass
|
|
// should declare the other operand as one of its super classes.
|
|
AsmOperandClass ParserMatchClass = ImmAsmOperand;
|
|
}
|
|
|
|
class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
|
|
: DAGOperand {
|
|
// RegClass - The register class of the operand.
|
|
RegisterClass RegClass = regclass;
|
|
// PrintMethod - The target method to call to print register operands of
|
|
// this type. The method normally will just use an alt-name index to look
|
|
// up the name to print. Default to the generic printOperand().
|
|
string PrintMethod = pm;
|
|
// ParserMatchClass - The "match class" that operands of this type fit
|
|
// in. Match classes are used to define the order in which instructions are
|
|
// match, to ensure that which instructions gets matched is deterministic.
|
|
//
|
|
// The target specific parser must be able to classify an parsed operand into
|
|
// a unique class, which does not partially overlap with any other classes. It
|
|
// can match a subset of some other class, in which case the AsmOperandClass
|
|
// should declare the other operand as one of its super classes.
|
|
AsmOperandClass ParserMatchClass;
|
|
|
|
string OperandNamespace = "MCOI";
|
|
string OperandType = "OPERAND_REGISTER";
|
|
}
|
|
|
|
let OperandType = "OPERAND_IMMEDIATE" in {
|
|
def i1imm : Operand<i1>;
|
|
def i8imm : Operand<i8>;
|
|
def i16imm : Operand<i16>;
|
|
def i32imm : Operand<i32>;
|
|
def i64imm : Operand<i64>;
|
|
|
|
def f32imm : Operand<f32>;
|
|
def f64imm : Operand<f64>;
|
|
}
|
|
|
|
/// zero_reg definition - Special node to stand for the zero register.
|
|
///
|
|
def zero_reg;
|
|
|
|
/// All operands which the MC layer classifies as predicates should inherit from
|
|
/// this class in some manner. This is already handled for the most commonly
|
|
/// used PredicateOperand, but may be useful in other circumstances.
|
|
class PredicateOp;
|
|
|
|
/// OperandWithDefaultOps - This Operand class can be used as the parent class
|
|
/// for an Operand that needs to be initialized with a default value if
|
|
/// no value is supplied in a pattern. This class can be used to simplify the
|
|
/// pattern definitions for instructions that have target specific flags
|
|
/// encoded as immediate operands.
|
|
class OperandWithDefaultOps<ValueType ty, dag defaultops>
|
|
: Operand<ty> {
|
|
dag DefaultOps = defaultops;
|
|
}
|
|
|
|
/// PredicateOperand - This can be used to define a predicate operand for an
|
|
/// instruction. OpTypes specifies the MIOperandInfo for the operand, and
|
|
/// AlwaysVal specifies the value of this predicate when set to "always
|
|
/// execute".
|
|
class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
|
|
: OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
|
|
let MIOperandInfo = OpTypes;
|
|
}
|
|
|
|
/// OptionalDefOperand - This is used to define a optional definition operand
|
|
/// for an instruction. DefaultOps is the register the operand represents if
|
|
/// none is supplied, e.g. zero_reg.
|
|
class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
|
|
: OperandWithDefaultOps<ty, defaultops> {
|
|
let MIOperandInfo = OpTypes;
|
|
}
|
|
|
|
|
|
// InstrInfo - This class should only be instantiated once to provide parameters
|
|
// which are global to the target machine.
|
|
//
|
|
class InstrInfo {
|
|
// Target can specify its instructions in either big or little-endian formats.
|
|
// For instance, while both Sparc and PowerPC are big-endian platforms, the
|
|
// Sparc manual specifies its instructions in the format [31..0] (big), while
|
|
// PowerPC specifies them using the format [0..31] (little).
|
|
bit isLittleEndianEncoding = 0;
|
|
|
|
// The instruction properties mayLoad, mayStore, and hasSideEffects are unset
|
|
// by default, and TableGen will infer their value from the instruction
|
|
// pattern when possible.
|
|
//
|
|
// Normally, TableGen will issue an error it it can't infer the value of a
|
|
// property that hasn't been set explicitly. When guessInstructionProperties
|
|
// is set, it will guess a safe value instead.
|
|
//
|
|
// This option is a temporary migration help. It will go away.
|
|
bit guessInstructionProperties = 1;
|
|
|
|
// TableGen's instruction encoder generator has support for matching operands
|
|
// to bit-field variables both by name and by position. While matching by
|
|
// name is preferred, this is currently not possible for complex operands,
|
|
// and some targets still reply on the positional encoding rules. When
|
|
// generating a decoder for such targets, the positional encoding rules must
|
|
// be used by the decoder generator as well.
|
|
//
|
|
// This option is temporary; it will go away once the TableGen decoder
|
|
// generator has better support for complex operands and targets have
|
|
// migrated away from using positionally encoded operands.
|
|
bit decodePositionallyEncodedOperands = 0;
|
|
|
|
// When set, this indicates that there will be no overlap between those
|
|
// operands that are matched by ordering (positional operands) and those
|
|
// matched by name.
|
|
//
|
|
// This option is temporary; it will go away once the TableGen decoder
|
|
// generator has better support for complex operands and targets have
|
|
// migrated away from using positionally encoded operands.
|
|
bit noNamedPositionallyEncodedOperands = 0;
|
|
}
|
|
|
|
// Standard Pseudo Instructions.
|
|
// This list must match TargetOpcodes.h and CodeGenTarget.cpp.
|
|
// Only these instructions are allowed in the TargetOpcode namespace.
|
|
let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
|
|
def PHI : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins variable_ops);
|
|
let AsmString = "PHINODE";
|
|
}
|
|
def INLINEASM : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins variable_ops);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0; // Note side effect is encoded in an operand.
|
|
}
|
|
def CFI_INSTRUCTION : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins i32imm:$id);
|
|
let AsmString = "";
|
|
let hasCtrlDep = 1;
|
|
let isNotDuplicable = 1;
|
|
}
|
|
def EH_LABEL : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins i32imm:$id);
|
|
let AsmString = "";
|
|
let hasCtrlDep = 1;
|
|
let isNotDuplicable = 1;
|
|
}
|
|
def GC_LABEL : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins i32imm:$id);
|
|
let AsmString = "";
|
|
let hasCtrlDep = 1;
|
|
let isNotDuplicable = 1;
|
|
}
|
|
def KILL : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins variable_ops);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0;
|
|
}
|
|
def EXTRACT_SUBREG : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0;
|
|
}
|
|
def INSERT_SUBREG : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0;
|
|
let Constraints = "$supersrc = $dst";
|
|
}
|
|
def IMPLICIT_DEF : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0;
|
|
let isReMaterializable = 1;
|
|
let isAsCheapAsAMove = 1;
|
|
}
|
|
def SUBREG_TO_REG : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0;
|
|
}
|
|
def COPY_TO_REGCLASS : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins unknown:$src, i32imm:$regclass);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0;
|
|
let isAsCheapAsAMove = 1;
|
|
}
|
|
def DBG_VALUE : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins variable_ops);
|
|
let AsmString = "DBG_VALUE";
|
|
let hasSideEffects = 0;
|
|
}
|
|
def REG_SEQUENCE : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins unknown:$supersrc, variable_ops);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0;
|
|
let isAsCheapAsAMove = 1;
|
|
}
|
|
def COPY : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins unknown:$src);
|
|
let AsmString = "";
|
|
let hasSideEffects = 0;
|
|
let isAsCheapAsAMove = 1;
|
|
}
|
|
def BUNDLE : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins variable_ops);
|
|
let AsmString = "BUNDLE";
|
|
}
|
|
def LIFETIME_START : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins i32imm:$id);
|
|
let AsmString = "LIFETIME_START";
|
|
let hasSideEffects = 0;
|
|
}
|
|
def LIFETIME_END : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins i32imm:$id);
|
|
let AsmString = "LIFETIME_END";
|
|
let hasSideEffects = 0;
|
|
}
|
|
def STACKMAP : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
|
|
let isCall = 1;
|
|
let mayLoad = 1;
|
|
let usesCustomInserter = 1;
|
|
}
|
|
def PATCHPOINT : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
|
|
i32imm:$nargs, i32imm:$cc, variable_ops);
|
|
let isCall = 1;
|
|
let mayLoad = 1;
|
|
let usesCustomInserter = 1;
|
|
}
|
|
def STATEPOINT : Instruction {
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins variable_ops);
|
|
let usesCustomInserter = 1;
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
let hasSideEffects = 1;
|
|
let isCall = 1;
|
|
}
|
|
def LOAD_STACK_GUARD : Instruction {
|
|
let OutOperandList = (outs ptr_rc:$dst);
|
|
let InOperandList = (ins);
|
|
let mayLoad = 1;
|
|
bit isReMaterializable = 1;
|
|
let hasSideEffects = 0;
|
|
bit isPseudo = 1;
|
|
}
|
|
def FRAME_ALLOC : Instruction {
|
|
// This instruction is really just a label. It has to be part of the chain so
|
|
// that it doesn't get dropped from the DAG, but it produces nothing and has
|
|
// no side effects.
|
|
let OutOperandList = (outs);
|
|
let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
|
|
let hasSideEffects = 0;
|
|
let hasCtrlDep = 1;
|
|
}
|
|
def FAULTING_LOAD_OP : Instruction {
|
|
let OutOperandList = (outs unknown:$dst);
|
|
let InOperandList = (ins variable_ops);
|
|
let usesCustomInserter = 1;
|
|
let mayLoad = 1;
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// AsmParser - This class can be implemented by targets that wish to implement
|
|
// .s file parsing.
|
|
//
|
|
// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
|
|
// syntax on X86 for example).
|
|
//
|
|
class AsmParser {
|
|
// AsmParserClassName - This specifies the suffix to use for the asmparser
|
|
// class. Generated AsmParser classes are always prefixed with the target
|
|
// name.
|
|
string AsmParserClassName = "AsmParser";
|
|
|
|
// AsmParserInstCleanup - If non-empty, this is the name of a custom member
|
|
// function of the AsmParser class to call on every matched instruction.
|
|
// This can be used to perform target specific instruction post-processing.
|
|
string AsmParserInstCleanup = "";
|
|
|
|
// ShouldEmitMatchRegisterName - Set to false if the target needs a hand
|
|
// written register name matcher
|
|
bit ShouldEmitMatchRegisterName = 1;
|
|
|
|
/// Does the instruction mnemonic allow '.'
|
|
bit MnemonicContainsDot = 0;
|
|
}
|
|
def DefaultAsmParser : AsmParser;
|
|
|
|
//===----------------------------------------------------------------------===//
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// AsmParserVariant - Subtargets can have multiple different assembly parsers
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// (e.g. AT&T vs Intel syntax on X86 for example). This class can be
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// implemented by targets to describe such variants.
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//
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class AsmParserVariant {
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// Variant - AsmParsers can be of multiple different variants. Variants are
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// used to support targets that need to parser multiple formats for the
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// assembly language.
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int Variant = 0;
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// Name - The AsmParser variant name (e.g., AT&T vs Intel).
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string Name = "";
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// CommentDelimiter - If given, the delimiter string used to recognize
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// comments which are hard coded in the .td assembler strings for individual
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// instructions.
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string CommentDelimiter = "";
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// RegisterPrefix - If given, the token prefix which indicates a register
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// token. This is used by the matcher to automatically recognize hard coded
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// register tokens as constrained registers, instead of tokens, for the
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// purposes of matching.
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string RegisterPrefix = "";
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}
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def DefaultAsmParserVariant : AsmParserVariant;
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/// AssemblerPredicate - This is a Predicate that can be used when the assembler
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/// matches instructions and aliases.
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class AssemblerPredicate<string cond, string name = ""> {
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bit AssemblerMatcherPredicate = 1;
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string AssemblerCondString = cond;
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string PredicateName = name;
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}
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/// TokenAlias - This class allows targets to define assembler token
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/// operand aliases. That is, a token literal operand which is equivalent
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/// to another, canonical, token literal. For example, ARM allows:
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/// vmov.u32 s4, #0 -> vmov.i32, #0
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/// 'u32' is a more specific designator for the 32-bit integer type specifier
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/// and is legal for any instruction which accepts 'i32' as a datatype suffix.
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/// def : TokenAlias<".u32", ".i32">;
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///
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/// This works by marking the match class of 'From' as a subclass of the
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/// match class of 'To'.
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class TokenAlias<string From, string To> {
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string FromToken = From;
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string ToToken = To;
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}
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/// MnemonicAlias - This class allows targets to define assembler mnemonic
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/// aliases. This should be used when all forms of one mnemonic are accepted
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/// with a different mnemonic. For example, X86 allows:
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/// sal %al, 1 -> shl %al, 1
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/// sal %ax, %cl -> shl %ax, %cl
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/// sal %eax, %cl -> shl %eax, %cl
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/// etc. Though "sal" is accepted with many forms, all of them are directly
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/// translated to a shl, so it can be handled with (in the case of X86, it
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/// actually has one for each suffix as well):
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/// def : MnemonicAlias<"sal", "shl">;
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///
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/// Mnemonic aliases are mapped before any other translation in the match phase,
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/// and do allow Requires predicates, e.g.:
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///
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/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
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/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
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///
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/// Mnemonic aliases can also be constrained to specific variants, e.g.:
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///
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/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
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///
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/// If no variant (e.g., "att" or "intel") is specified then the alias is
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/// applied unconditionally.
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class MnemonicAlias<string From, string To, string VariantName = ""> {
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string FromMnemonic = From;
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string ToMnemonic = To;
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string AsmVariantName = VariantName;
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// Predicates - Predicates that must be true for this remapping to happen.
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list<Predicate> Predicates = [];
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}
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/// InstAlias - This defines an alternate assembly syntax that is allowed to
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/// match an instruction that has a different (more canonical) assembly
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/// representation.
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class InstAlias<string Asm, dag Result, int Emit = 1> {
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string AsmString = Asm; // The .s format to match the instruction with.
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dag ResultInst = Result; // The MCInst to generate.
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// This determines which order the InstPrinter detects aliases for
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// printing. A larger value makes the alias more likely to be
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// emitted. The Instruction's own definition is notionally 0.5, so 0
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// disables printing and 1 enables it if there are no conflicting aliases.
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int EmitPriority = Emit;
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// Predicates - Predicates that must be true for this to match.
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list<Predicate> Predicates = [];
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// If the instruction specified in Result has defined an AsmMatchConverter
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// then setting this to 1 will cause the alias to use the AsmMatchConverter
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// function when converting the OperandVector into an MCInst instead of the
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// function that is generated by the dag Result.
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// Setting this to 0 will cause the alias to ignore the Result instruction's
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// defined AsmMatchConverter and instead use the function generated by the
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// dag Result.
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bit UseInstAsmMatchConverter = 1;
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}
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//===----------------------------------------------------------------------===//
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// AsmWriter - This class can be implemented by targets that need to customize
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// the format of the .s file writer.
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//
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// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
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// on X86 for example).
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//
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class AsmWriter {
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// AsmWriterClassName - This specifies the suffix to use for the asmwriter
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// class. Generated AsmWriter classes are always prefixed with the target
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// name.
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string AsmWriterClassName = "InstPrinter";
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// PassSubtarget - Determines whether MCSubtargetInfo should be passed to
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// the various print methods.
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// FIXME: Remove after all ports are updated.
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int PassSubtarget = 0;
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// Variant - AsmWriters can be of multiple different variants. Variants are
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// used to support targets that need to emit assembly code in ways that are
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// mostly the same for different targets, but have minor differences in
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// syntax. If the asmstring contains {|} characters in them, this integer
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// will specify which alternative to use. For example "{x|y|z}" with Variant
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// == 1, will expand to "y".
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int Variant = 0;
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}
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def DefaultAsmWriter : AsmWriter;
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|
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//===----------------------------------------------------------------------===//
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// Target - This class contains the "global" target information
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//
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class Target {
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// InstructionSet - Instruction set description for this target.
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InstrInfo InstructionSet;
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// AssemblyParsers - The AsmParser instances available for this target.
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list<AsmParser> AssemblyParsers = [DefaultAsmParser];
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/// AssemblyParserVariants - The AsmParserVariant instances available for
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/// this target.
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list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
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// AssemblyWriters - The AsmWriter instances available for this target.
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list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
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}
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//===----------------------------------------------------------------------===//
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// SubtargetFeature - A characteristic of the chip set.
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//
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class SubtargetFeature<string n, string a, string v, string d,
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list<SubtargetFeature> i = []> {
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// Name - Feature name. Used by command line (-mattr=) to determine the
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// appropriate target chip.
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//
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string Name = n;
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// Attribute - Attribute to be set by feature.
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//
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string Attribute = a;
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// Value - Value the attribute to be set to by feature.
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//
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string Value = v;
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// Desc - Feature description. Used by command line (-mattr=) to display help
|
|
// information.
|
|
//
|
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string Desc = d;
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// Implies - Features that this feature implies are present. If one of those
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// features isn't set, then this one shouldn't be set either.
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//
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list<SubtargetFeature> Implies = i;
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}
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/// Specifies a Subtarget feature that this instruction is deprecated on.
|
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class Deprecated<SubtargetFeature dep> {
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SubtargetFeature DeprecatedFeatureMask = dep;
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}
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|
|
/// A custom predicate used to determine if an instruction is
|
|
/// deprecated or not.
|
|
class ComplexDeprecationPredicate<string dep> {
|
|
string ComplexDeprecationPredicate = dep;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Processor chip sets - These values represent each of the chip sets supported
|
|
// by the scheduler. Each Processor definition requires corresponding
|
|
// instruction itineraries.
|
|
//
|
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class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
|
|
// Name - Chip set name. Used by command line (-mcpu=) to determine the
|
|
// appropriate target chip.
|
|
//
|
|
string Name = n;
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|
|
// SchedModel - The machine model for scheduling and instruction cost.
|
|
//
|
|
SchedMachineModel SchedModel = NoSchedModel;
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|
|
// ProcItin - The scheduling information for the target processor.
|
|
//
|
|
ProcessorItineraries ProcItin = pi;
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|
|
// Features - list of
|
|
list<SubtargetFeature> Features = f;
|
|
}
|
|
|
|
// ProcessorModel allows subtargets to specify the more general
|
|
// SchedMachineModel instead if a ProcessorItinerary. Subtargets will
|
|
// gradually move to this newer form.
|
|
//
|
|
// Although this class always passes NoItineraries to the Processor
|
|
// class, the SchedMachineModel may still define valid Itineraries.
|
|
class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
|
|
: Processor<n, NoItineraries, f> {
|
|
let SchedModel = m;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// InstrMapping - This class is used to create mapping tables to relate
|
|
// instructions with each other based on the values specified in RowFields,
|
|
// ColFields, KeyCol and ValueCols.
|
|
//
|
|
class InstrMapping {
|
|
// FilterClass - Used to limit search space only to the instructions that
|
|
// define the relationship modeled by this InstrMapping record.
|
|
string FilterClass;
|
|
|
|
// RowFields - List of fields/attributes that should be same for all the
|
|
// instructions in a row of the relation table. Think of this as a set of
|
|
// properties shared by all the instructions related by this relationship
|
|
// model and is used to categorize instructions into subgroups. For instance,
|
|
// if we want to define a relation that maps 'Add' instruction to its
|
|
// predicated forms, we can define RowFields like this:
|
|
//
|
|
// let RowFields = BaseOp
|
|
// All add instruction predicated/non-predicated will have to set their BaseOp
|
|
// to the same value.
|
|
//
|
|
// def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
|
|
// def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
|
|
// def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
|
|
list<string> RowFields = [];
|
|
|
|
// List of fields/attributes that are same for all the instructions
|
|
// in a column of the relation table.
|
|
// Ex: let ColFields = 'predSense' -- It means that the columns are arranged
|
|
// based on the 'predSense' values. All the instruction in a specific
|
|
// column have the same value and it is fixed for the column according
|
|
// to the values set in 'ValueCols'.
|
|
list<string> ColFields = [];
|
|
|
|
// Values for the fields/attributes listed in 'ColFields'.
|
|
// Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
|
|
// that models this relation) should be non-predicated.
|
|
// In the example above, 'Add' is the key instruction.
|
|
list<string> KeyCol = [];
|
|
|
|
// List of values for the fields/attributes listed in 'ColFields', one for
|
|
// each column in the relation table.
|
|
//
|
|
// Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
|
|
// table. First column requires all the instructions to have predSense
|
|
// set to 'true' and second column requires it to be 'false'.
|
|
list<list<string> > ValueCols = [];
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pull in the common support for calling conventions.
|
|
//
|
|
include "llvm/Target/TargetCallingConv.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pull in the common support for DAG isel generation.
|
|
//
|
|
include "llvm/Target/TargetSelectionDAG.td"
|