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https://github.com/c64scene-ar/llvm-6502.git
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cf0fa9b9dd
The z13 vector facility includes some instructions that operate only on the high f64 in a v2f64, effectively extending the FP register set from 16 to 32 registers. It's still better to use the old instructions if the operands happen to fit though, since the older instructions have a shorter encoding. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236524 91177308-0d34-0410-b5e6-96231b3b80d8
420 lines
18 KiB
TableGen
420 lines
18 KiB
TableGen
//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Select instructions
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//===----------------------------------------------------------------------===//
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// C's ?: operator for floating-point operands.
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def SelectF32 : SelectWrapper<FP32>;
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def SelectF64 : SelectWrapper<FP64>;
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def SelectF128 : SelectWrapper<FP128>;
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defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
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nonvolatile_load, bdxaddr20only>;
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defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
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nonvolatile_load, bdxaddr20only>;
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//===----------------------------------------------------------------------===//
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// Move instructions
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//===----------------------------------------------------------------------===//
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// Load zero.
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let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
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def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
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def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
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}
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// Moves between two floating-point registers.
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let hasSideEffects = 0 in {
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def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>;
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def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
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def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
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}
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// Moves between two floating-point registers that also set the condition
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// codes.
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let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
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defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
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defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
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defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
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}
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// Note that the comparison against zero operation is not available if we
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// have vector support, since load-and-test instructions will partially
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// clobber the target (vector) register.
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let Predicates = [FeatureNoVector] in {
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defm : CompareZeroFP<LTEBRCompare, FP32>;
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defm : CompareZeroFP<LTDBRCompare, FP64>;
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defm : CompareZeroFP<LTXBRCompare, FP128>;
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}
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// Moves between 64-bit integer and floating-point registers.
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def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
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def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
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// fcopysign with an FP32 result.
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let isCodeGenOnly = 1 in {
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def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
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def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
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}
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// The sign of an FP128 is in the high register.
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def : Pat<(fcopysign FP32:$src1, FP128:$src2),
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(CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
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// fcopysign with an FP64 result.
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let isCodeGenOnly = 1 in
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def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
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def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
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// The sign of an FP128 is in the high register.
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def : Pat<(fcopysign FP64:$src1, FP128:$src2),
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(CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
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// fcopysign with an FP128 result. Use "upper" as the high half and leave
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// the low half as-is.
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class CopySign128<RegisterOperand cls, dag upper>
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: Pat<(fcopysign FP128:$src1, cls:$src2),
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(INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
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def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),
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FP32:$src2)>;
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def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
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FP64:$src2)>;
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def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
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(EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
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defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>;
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defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>;
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defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
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//===----------------------------------------------------------------------===//
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// Load instructions
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//===----------------------------------------------------------------------===//
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let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
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defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
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defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
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// For z13 we prefer LDE over LE to avoid partial register dependencies.
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def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;
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// These instructions are split after register allocation, so we don't
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// want a custom inserter.
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let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
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def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
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[(set FP128:$dst, (load bdxaddr20only128:$src))]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Store instructions
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//===----------------------------------------------------------------------===//
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let SimpleBDXStore = 1 in {
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defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
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defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
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// These instructions are split after register allocation, so we don't
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// want a custom inserter.
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let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
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def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
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[(store FP128:$src, bdxaddr20only128:$dst)]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Conversion instructions
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//===----------------------------------------------------------------------===//
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// Convert floating-point values to narrower representations, rounding
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// according to the current mode. The destination of LEXBR and LDXBR
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// is a 128-bit value, but only the first register of the pair is used.
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def LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>;
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def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
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def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
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def LEDBRA : UnaryRRF4<"ledbra", 0xB344, FP32, FP64>,
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Requires<[FeatureFPExtension]>;
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def LEXBRA : UnaryRRF4<"lexbra", 0xB346, FP128, FP128>,
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Requires<[FeatureFPExtension]>;
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def LDXBRA : UnaryRRF4<"ldxbra", 0xB345, FP128, FP128>,
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Requires<[FeatureFPExtension]>;
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def : Pat<(f32 (fround FP128:$src)),
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(EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>;
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def : Pat<(f64 (fround FP128:$src)),
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(EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
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// Extend register floating-point values to wider representations.
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def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>;
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def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>;
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def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>;
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// Extend memory floating-point values to wider representations.
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def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>;
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def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>;
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def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
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// Convert a signed integer register value to a floating-point one.
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def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>;
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def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>;
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def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
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def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>;
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def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>;
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def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
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// Convert am unsigned integer register value to a floating-point one.
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let Predicates = [FeatureFPExtension] in {
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def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32, GR32>;
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def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64, GR32>;
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def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>;
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def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32, GR64>;
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def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64, GR64>;
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def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>;
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def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
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def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
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def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
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def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;
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def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;
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def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;
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}
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// Convert a floating-point register value to a signed integer value,
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// with the second operand (modifier M3) specifying the rounding mode.
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let Defs = [CC] in {
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def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
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def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
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def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
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def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
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def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
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def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
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}
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// fp_to_sint always rounds towards zero, which is modifier value 5.
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def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>;
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def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>;
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def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
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def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;
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def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;
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def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
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// Convert a floating-point register value to an unsigned integer value.
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let Predicates = [FeatureFPExtension] in {
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let Defs = [CC] in {
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def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>;
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def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>;
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def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>;
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def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>;
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def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>;
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def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>;
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}
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def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>;
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def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>;
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def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>;
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def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>;
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def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>;
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def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>;
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}
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//===----------------------------------------------------------------------===//
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// Unary arithmetic
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//===----------------------------------------------------------------------===//
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// Negation (Load Complement).
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let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
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def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32, FP32>;
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def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64, FP64>;
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def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
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}
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// Absolute value (Load Positive).
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let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
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def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32, FP32>;
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def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64, FP64>;
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def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
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}
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// Negative absolute value (Load Negative).
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let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
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def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32, FP32>;
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def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64, FP64>;
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def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
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}
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// Square root.
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def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>;
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def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>;
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def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
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def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
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def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
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// Round to an integer, with the second operand (modifier M3) specifying
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// the rounding mode. These forms always check for inexact conditions.
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def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>;
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def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>;
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def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
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// frint rounds according to the current mode (modifier 0) and detects
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// inexact conditions.
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def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
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def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
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def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
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let Predicates = [FeatureFPExtension] in {
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// Extended forms of the FIxBR instructions. M4 can be set to 4
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// to suppress detection of inexact conditions.
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def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>;
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def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>;
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def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>;
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// fnearbyint is like frint but does not detect inexact conditions.
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def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>;
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def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>;
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def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;
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// floor is no longer allowed to raise an inexact condition,
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// so restrict it to the cases where the condition can be suppressed.
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// Mode 7 is round towards -inf.
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def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>;
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def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>;
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def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;
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// Same idea for ceil, where mode 6 is round towards +inf.
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def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>;
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def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>;
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def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;
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// Same idea for trunc, where mode 5 is round towards zero.
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def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>;
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def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>;
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def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;
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// Same idea for round, where mode 1 is round towards nearest with
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// ties away from zero.
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def : Pat<(frnd FP32:$src), (FIEBRA 1, FP32:$src, 4)>;
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def : Pat<(frnd FP64:$src), (FIDBRA 1, FP64:$src, 4)>;
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def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>;
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}
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//===----------------------------------------------------------------------===//
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// Binary arithmetic
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//===----------------------------------------------------------------------===//
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// Addition.
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let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
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let isCommutable = 1 in {
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def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>;
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def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>;
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def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
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}
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def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
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def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
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}
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// Subtraction.
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let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
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def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>;
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def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>;
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def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
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def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>;
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def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>;
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}
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// Multiplication.
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let isCommutable = 1 in {
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def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>;
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def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>;
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def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>;
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}
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def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
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def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>;
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// f64 multiplication of two FP32 registers.
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def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
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def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
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(MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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FP32:$src1, subreg_r32), FP32:$src2)>;
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// f64 multiplication of an FP32 register and an f32 memory.
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def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
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def : Pat<(fmul (f64 (fextend FP32:$src1)),
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(f64 (extloadf32 bdxaddr12only:$addr))),
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(MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32),
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bdxaddr12only:$addr)>;
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// f128 multiplication of two FP64 registers.
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def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
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def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
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(MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
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FP64:$src1, subreg_h64), FP64:$src2)>;
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// f128 multiplication of an FP64 register and an f64 memory.
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def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
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def : Pat<(fmul (f128 (fextend FP64:$src1)),
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(f128 (extloadf64 bdxaddr12only:$addr))),
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(MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
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bdxaddr12only:$addr)>;
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// Fused multiply-add.
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def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
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def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
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def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
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def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
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// Fused multiply-subtract.
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def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
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def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
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def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
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def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
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// Division.
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def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>;
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def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>;
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def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
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def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
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def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
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//===----------------------------------------------------------------------===//
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// Comparisons
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//===----------------------------------------------------------------------===//
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let Defs = [CC], CCValues = 0xF in {
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def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32, FP32>;
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def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64, FP64>;
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def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>;
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def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>;
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def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
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}
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//===----------------------------------------------------------------------===//
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// Peepholes
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//===----------------------------------------------------------------------===//
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def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>;
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def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>;
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def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;
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