Evan Cheng 1887c1c2f9 Fix a number of byval / memcpy / memset related codegen issues. ...

1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55139 91177308-0d34-0410-b5e6-96231b3b80d8

2008-08-21 21:00:15 +00:00

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Alpha

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ARM

It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.

2008-08-08 06:56:16 +00:00

CBackend

In the CBackend, use casts to force integer add, subtract, and

2008-07-18 18:43:12 +00:00

CellSPU

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CPP

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Generic

Improve support for vector casts in LLVM IR and CodeGen.

2008-08-14 20:04:46 +00:00

IA64

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Mips

Support added for ctlz intrinsic, test case added.

2008-08-08 06:16:31 +00:00

PowerPC

Fix a catastrophic PPC64 ABI bug: i32 operands which are passed in memory (all of the parameter registers are used) are loaded from sp offsets that were off by 4.

2008-07-24 08:17:07 +00:00

SPARC

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X86

Fix a number of byval / memcpy / memset related codegen issues.

2008-08-21 21:00:15 +00:00