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d950941e13
Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
1.1 KiB
TableGen
35 lines
1.1 KiB
TableGen
//===--- BlackfinInstrFormats.td ---------------------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class InstBfin<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<32> Inst;
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let Namespace = "BF";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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// Single-word (16-bit) instructions
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class F1<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstBfin<outs, ins, asmstr, pattern> {
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}
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// Double-word (32-bit) instructions
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class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstBfin<outs, ins, asmstr, pattern> {
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}
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