Colin LeMahieu 189606dbfe [Hexagon] Adding add reg, imm form with encoding bits and test. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223504 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-05 19:51:23 +00:00
..
Analysis	BFI: Saturate when combining edges to a successor	2014-12-05 19:13:42 +00:00
AsmParser
Bitcode	Ask the module for its the identified types.	2014-12-03 07:18:23 +00:00
CodeGen	These two calls were grabbing the same register info. Unify them.	2014-12-05 19:23:55 +00:00
DebugInfo
ExecutionEngine
IR	Fix a bug when pretty-printing DW_OP_deref.	2014-12-05 18:19:38 +00:00
IRReader
LineEditor
Linker	Remove unused arguments. NFC.	2014-12-05 19:35:07 +00:00
LTO
MC	clang-formatted ranged loops and assignment, NFC.	2014-12-04 08:30:39 +00:00
Object	Add mach-o LC_RPATH support to llvm-objdump	2014-12-04 07:37:02 +00:00
Option
ProfileData
Support	Silence warning: variable 'buffer' set but not used.	2014-12-04 21:36:38 +00:00
TableGen
Target	[Hexagon] Adding add reg, imm form with encoding bits and test.	2014-12-05 19:51:23 +00:00
Transforms	[msan] Avoid extra origin address realignment.	2014-12-05 14:34:03 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile