Colin LeMahieu 189606dbfe [Hexagon] Adding add reg, imm form with encoding bits and test. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223504 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-05 19:51:23 +00:00
..
AArch64	Update AArch64 ELF relocations to ABI 1.0	2014-11-26 10:49:18 +00:00
ARM	Improvements to ARM assembler tests	2014-12-05 16:33:56 +00:00
AsmParser
COFF
Disassembler	[Hexagon] Adding add reg, imm form with encoding bits and test.	2014-12-05 19:51:23 +00:00
ELF	Commit back the correct bits of r222760 (was r222538).	2014-11-27 17:13:56 +00:00
Hexagon	[Hexagon] Adding cmp* immediate form instructions.	2014-11-26 19:43:12 +00:00
MachO
Markup
Mips	The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.	2014-12-01 11:12:04 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
R600	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
Sparc
SystemZ
X86	[X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80.	2014-12-03 02:03:26 +00:00