llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-26 10:29:36 +00:00

History

Reed Kotler 18afdb3210 Add logical ops to Mips fast-isel

Summary:
Code is mostly copied from AArch64 port and modified where needed for Mips.

This handles the "non" legal cases of logical ops. Legal cases are handled by tablegen patterns.

Test Plan:
Make check test logopm.ll

All of test-suite passes at O0/O2 and mips32 r1/r2 with this new change.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: echristo, llvm-commits, aemerson, rfuhler

Differential Revision: http://reviews.llvm.org/D6599

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231665 91177308-0d34-0410-b5e6-96231b3b80d8

2015-03-09 16:28:10 +00:00

AArch64

[AArch64][LoadStoreOptimizer] Generate LDP + SXTW instead of LD[U]R + LD[U]RSW.

2015-03-06 22:42:10 +00:00

ARM

Remove use of misched-bench from this test and replace it with

2015-03-07 01:39:06 +00:00

BPF

…

CPP

…

Generic