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https://github.com/c64scene-ar/llvm-6502.git
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9de5d0dd42
- Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45851 91177308-0d34-0410-b5e6-96231b3b80d8
139 lines
6.0 KiB
C++
139 lines
6.0 KiB
C++
//===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Cell SPU uses to lower LLVM code into
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// a selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPU_ISELLOWERING_H
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#define SPU_ISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "SPU.h"
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namespace llvm {
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namespace SPUISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+SPU::INSTRUCTION_LIST_END,
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// Pseudo instructions:
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RET_FLAG, ///< Return with flag, matched by bi instruction
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Hi, ///< High address component (upper 16)
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Lo, ///< Low address component (lower 16)
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PCRelAddr, ///< Program counter relative address
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AFormAddr, ///< A-form address (local store)
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DFormAddr, ///< D-Form address "imm($r)"
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XFormAddr, ///< X-Form address "$r($r)"
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LDRESULT, ///< Load result (value, chain)
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CALL, ///< CALL instruction
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SHUFB, ///< Vector shuffle (permute)
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INSERT_MASK, ///< Insert element shuffle mask
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CNTB, ///< Count leading ones in bytes
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PROMOTE_SCALAR, ///< Promote scalar->vector
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EXTRACT_ELT0, ///< Extract element 0
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EXTRACT_ELT0_CHAINED, ///< Extract element 0, with chain
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EXTRACT_I1_ZEXT, ///< Extract element 0 as i1, zero extend
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EXTRACT_I1_SEXT, ///< Extract element 0 as i1, sign extend
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EXTRACT_I8_ZEXT, ///< Extract element 0 as i8, zero extend
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EXTRACT_I8_SEXT, ///< Extract element 0 as i8, sign extend
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MPY, ///< 16-bit Multiply (low parts of a 32-bit)
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MPYU, ///< Multiply Unsigned
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MPYH, ///< Multiply High
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MPYHH, ///< Multiply High-High
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VEC_SHL, ///< Vector shift left
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VEC_SRL, ///< Vector shift right (logical)
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VEC_SRA, ///< Vector shift right (arithmetic)
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VEC_ROTL, ///< Vector rotate left
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VEC_ROTR, ///< Vector rotate right
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ROTBYTES_RIGHT_Z, ///< Vector rotate right, by bytes, zero fill
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ROTBYTES_RIGHT_S, ///< Vector rotate right, by bytes, sign fill
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ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
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ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain
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FSMBI, ///< Form Select Mask for Bytes, Immediate
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SELB, ///< Select bits -> (b & mask) | (a & ~mask)
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SFPConstant, ///< Single precision floating point constant
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FPInterp, ///< Floating point interpolate
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FPRecipEst, ///< Floating point reciprocal estimate
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SEXT32TO64, ///< Sign-extended 32-bit const -> 64-bits
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LAST_SPUISD ///< Last user-defined instruction
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};
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}
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/// Predicates that are used for node matching:
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namespace SPU {
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SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
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MVT::ValueType ValueType);
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SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
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MVT::ValueType ValueType);
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SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
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MVT::ValueType ValueType);
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SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
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MVT::ValueType ValueType);
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SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
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MVT::ValueType ValueType);
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SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
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SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
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}
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class SPUTargetMachine; // forward dec'l.
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class SPUTargetLowering :
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public TargetLowering
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{
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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int ReturnAddrIndex; // FrameIndex for return slot.
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SPUTargetMachine &SPUTM;
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public:
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SPUTargetLowering(SPUTargetMachine &TM);
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/// getTargetNodeName() - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
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uint64_t Mask,
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uint64_t &KnownZero,
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uint64_t &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
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std::vector<SDOperand> &Ops,
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SelectionDAG &DAG);
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode.
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virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
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virtual bool isLegalAddressImmediate(GlobalValue *) const;
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};
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}
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#endif
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