6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-24 22:32:47 +00:00
Code Issues Projects Releases Wiki Activity
18c8166405
llvm-6502/test/CodeGen/R600/mad-sub.ll
Tom Stellard 1f996fa36b R600/SI: Add a stub GCNTargetMachine 
This is equivalent to the AMDGPUTargetMachine now, but it is the
starting point for separating R600 and GCN functionality into separate
targets.

It is recommened that users start using the gcn triple for GCN-based
GPUs, because using the r600 triple for these GPUs will be deprecated in
the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-06 18:00:21 +00:00

216 lines
9.1 KiB
LLVM
Raw Blame History

; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() #0
declare float @llvm.fabs.f32(float) #0
; FUNC-LABEL: {{^}}mad_sub_f32:
; SI: buffer_load_dword [[REGA:v[0-9]+]]
; SI: buffer_load_dword [[REGB:v[0-9]+]]
; SI: buffer_load_dword [[REGC:v[0-9]+]]
; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]]
; SI: buffer_store_dword [[RESULT]]
define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
%tid.ext = sext i32 %tid to i64
%gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
%add1 = add i64 %tid.ext, 1
%gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
%add2 = add i64 %tid.ext, 2
%gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
%outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
%a = load float addrspace(1)* %gep0, align 4
%b = load float addrspace(1)* %gep1, align 4
%c = load float addrspace(1)* %gep2, align 4
%mul = fmul float %a, %b
%sub = fsub float %mul, %c
store float %sub, float addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: {{^}}mad_sub_inv_f32:
; SI: buffer_load_dword [[REGA:v[0-9]+]]
; SI: buffer_load_dword [[REGB:v[0-9]+]]
; SI: buffer_load_dword [[REGC:v[0-9]+]]
; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
; SI: buffer_store_dword [[RESULT]]
define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
%tid.ext = sext i32 %tid to i64
%gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
%add1 = add i64 %tid.ext, 1
%gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
%add2 = add i64 %tid.ext, 2
%gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
%outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
%a = load float addrspace(1)* %gep0, align 4
%b = load float addrspace(1)* %gep1, align 4
%c = load float addrspace(1)* %gep2, align 4
%mul = fmul float %a, %b
%sub = fsub float %c, %mul
store float %sub, float addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: {{^}}mad_sub_f64:
; SI: v_mul_f64
; SI: v_add_f64
define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double addrspace(1)* noalias nocapture readonly %ptr) #1 {
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
%tid.ext = sext i32 %tid to i64
%gep0 = getelementptr double addrspace(1)* %ptr, i64 %tid.ext
%add1 = add i64 %tid.ext, 1
%gep1 = getelementptr double addrspace(1)* %ptr, i64 %add1
%add2 = add i64 %tid.ext, 2
%gep2 = getelementptr double addrspace(1)* %ptr, i64 %add2
%outgep = getelementptr double addrspace(1)* %out, i64 %tid.ext
%a = load double addrspace(1)* %gep0, align 8
%b = load double addrspace(1)* %gep1, align 8
%c = load double addrspace(1)* %gep2, align 8
%mul = fmul double %a, %b
%sub = fsub double %mul, %c
store double %sub, double addrspace(1)* %outgep, align 8
ret void
}
; FUNC-LABEL: {{^}}mad_sub_fabs_f32:
; SI: buffer_load_dword [[REGA:v[0-9]+]]
; SI: buffer_load_dword [[REGB:v[0-9]+]]
; SI: buffer_load_dword [[REGC:v[0-9]+]]
; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]|
; SI: buffer_store_dword [[RESULT]]
define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
%tid.ext = sext i32 %tid to i64
%gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
%add1 = add i64 %tid.ext, 1
%gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
%add2 = add i64 %tid.ext, 2
%gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
%outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
%a = load float addrspace(1)* %gep0, align 4
%b = load float addrspace(1)* %gep1, align 4
%c = load float addrspace(1)* %gep2, align 4
%c.abs = call float @llvm.fabs.f32(float %c) #0
%mul = fmul float %a, %b
%sub = fsub float %mul, %c.abs
store float %sub, float addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: {{^}}mad_sub_fabs_inv_f32:
; SI: buffer_load_dword [[REGA:v[0-9]+]]
; SI: buffer_load_dword [[REGB:v[0-9]+]]
; SI: buffer_load_dword [[REGC:v[0-9]+]]
; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]|
; SI: buffer_store_dword [[RESULT]]
define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
%tid.ext = sext i32 %tid to i64
%gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
%add1 = add i64 %tid.ext, 1
%gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
%add2 = add i64 %tid.ext, 2
%gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
%outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
%a = load float addrspace(1)* %gep0, align 4
%b = load float addrspace(1)* %gep1, align 4
%c = load float addrspace(1)* %gep2, align 4
%c.abs = call float @llvm.fabs.f32(float %c) #0
%mul = fmul float %a, %b
%sub = fsub float %c.abs, %mul
store float %sub, float addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: {{^}}neg_neg_mad_f32:
; SI: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
%tid.ext = sext i32 %tid to i64
%gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
%add1 = add i64 %tid.ext, 1
%gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
%add2 = add i64 %tid.ext, 2
%gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
%outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
%a = load float addrspace(1)* %gep0, align 4
%b = load float addrspace(1)* %gep1, align 4
%c = load float addrspace(1)* %gep2, align 4
%nega = fsub float -0.000000e+00, %a
%negb = fsub float -0.000000e+00, %b
%mul = fmul float %nega, %negb
%sub = fadd float %mul, %c
store float %sub, float addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: {{^}}mad_fabs_sub_f32:
; SI: buffer_load_dword [[REGA:v[0-9]+]]
; SI: buffer_load_dword [[REGB:v[0-9]+]]
; SI: buffer_load_dword [[REGC:v[0-9]+]]
; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]]
; SI: buffer_store_dword [[RESULT]]
define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 {
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
%tid.ext = sext i32 %tid to i64
%gep0 = getelementptr float addrspace(1)* %ptr, i64 %tid.ext
%add1 = add i64 %tid.ext, 1
%gep1 = getelementptr float addrspace(1)* %ptr, i64 %add1
%add2 = add i64 %tid.ext, 2
%gep2 = getelementptr float addrspace(1)* %ptr, i64 %add2
%outgep = getelementptr float addrspace(1)* %out, i64 %tid.ext
%a = load float addrspace(1)* %gep0, align 4
%b = load float addrspace(1)* %gep1, align 4
%c = load float addrspace(1)* %gep2, align 4
%b.abs = call float @llvm.fabs.f32(float %b) #0
%mul = fmul float %a, %b.abs
%sub = fsub float %mul, %c
store float %sub, float addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: {{^}}fsub_c_fadd_a_a:
; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI: v_mad_f32 [[RESULT:v[0-9]+]], -2.0, [[R1]], [[R2]]
; SI: buffer_store_dword [[RESULT]]
define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in) {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
%r1 = load float addrspace(1)* %gep.0
%r2 = load float addrspace(1)* %gep.1
%add = fadd float %r1, %r1
%r3 = fsub float %r2, %add
store float %r3, float addrspace(1)* %gep.out
ret void
}
; FUNC-LABEL: {{^}}fsub_fadd_a_a_c:
; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]]
; SI: buffer_store_dword [[RESULT]]
define void @fsub_fadd_a_a_c(float addrspace(1)* %out, float addrspace(1)* %in) {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
%r1 = load float addrspace(1)* %gep.0
%r2 = load float addrspace(1)* %gep.1
%add = fadd float %r1, %r1
%r3 = fsub float %add, %r2
store float %r3, float addrspace(1)* %gep.out
ret void
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
Reference in New Issue View Git Blame Copy Permalink