llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-05 13:09:10 +00:00

History

Eli Bendersky 700ed80d3d Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-21 20:05:00 +00:00
..
MCTargetDesc	Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and explicitly set this in every target that needs to change it from the default.	2013-01-23 16:22:04 +00:00
TargetInfo	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
CMakeLists.txt
DelaySlotFiller.cpp
FPMover.cpp
LLVMBuild.txt
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp
SparcCallingConv.td
SparcFrameLowering.cpp	Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo	2013-02-21 20:05:00 +00:00
SparcFrameLowering.h	Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo	2013-02-21 20:05:00 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td	Move MRI liveouts to Sparc return instructions.	2013-02-05 18:16:58 +00:00
SparcISelDAGToDAG.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
SparcISelLowering.cpp	Move MRI liveouts to Sparc return instructions.	2013-02-05 18:16:58 +00:00
SparcISelLowering.h
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp	Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo	2013-02-21 20:05:00 +00:00
SparcRegisterInfo.h	Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo	2013-02-21 20:05:00 +00:00
SparcRegisterInfo.td
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetMachine.cpp	Switch TargetTransformInfo from an immutable analysis pass that requires	2013-01-07 01:37:14 +00:00
SparcTargetMachine.h	Switch TargetTransformInfo from an immutable analysis pass that requires	2013-01-07 01:37:14 +00:00

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support