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https://github.com/c64scene-ar/llvm-6502.git
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1911fd4f85
This pass: 1. Splits TargetMachine into TargetMachine (generic targets, can be implemented any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by things using libcodegen and other support). 2. Instead of having each target fully populate the passmgr for file or JIT output, move all this to common code, and give targets hooks they can implement. 3. Commonalize the target population stuff between file emission and JIT emission. 4. All (native code) codegen stuff now happens in a FunctionPassManager, which paves the way for "fast -O0" stuff in the CFE later, and now LLC could lazily stream .bc files from disk to use less memory. 5. There are now many fewer #includes and the targets don't depend on the scalar xforms or libanalysis anymore (but codegen does). 6. Changing common code generator pass ordering stuff no longer requires touching all targets. 7. The JIT now has the option of "-fast" codegen or normal optimized codegen, which is now orthogonal to the fact that JIT'ing is being done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30081 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
4.6 KiB
C++
144 lines
4.6 KiB
C++
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCTargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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using namespace llvm;
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namespace {
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// Register the targets
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RegisterTarget<PPC32TargetMachine>
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X("ppc32", " PowerPC 32");
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RegisterTarget<PPC64TargetMachine>
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Y("ppc64", " PowerPC 64");
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}
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unsigned PPC32TargetMachine::getJITMatchQuality() {
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#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
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if (sizeof(void*) == 4)
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return 10;
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#endif
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return 0;
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}
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unsigned PPC64TargetMachine::getJITMatchQuality() {
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#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
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if (sizeof(void*) == 8)
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return 10;
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#endif
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return 0;
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}
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unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "powerpc-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
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return 20;
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer32)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "powerpc64-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 10 && std::string(TT.begin(), TT.begin()+10) == "powerpc64-")
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return 20;
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer64)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
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bool is64Bit)
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: Subtarget(M, FS, is64Bit),
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DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
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FrameInfo(*this, false), JITInfo(*this, is64Bit), TLInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()) {
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if (getRelocationModel() == Reloc::Default)
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if (Subtarget.isDarwin())
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setRelocationModel(Reloc::DynamicNoPIC);
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else
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setRelocationModel(Reloc::PIC_);
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}
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PPC32TargetMachine::PPC32TargetMachine(const Module &M, const std::string &FS)
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: PPCTargetMachine(M, FS, false) {
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}
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PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS)
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: PPCTargetMachine(M, FS, true) {
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool PPCTargetMachine::addInstSelector(FunctionPassManager &PM, bool Fast) {
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// Install an instruction selector.
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PM.add(createPPCISelDag(*this));
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return false;
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}
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bool PPCTargetMachine::addPreEmitPass(FunctionPassManager &PM, bool Fast) {
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// Must run branch selection immediately preceding the asm printer.
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PM.add(createPPCBranchSelectionPass());
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return false;
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}
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bool PPCTargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
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std::ostream &Out) {
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PM.add(createDarwinAsmPrinter(Out, *this));
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return false;
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}
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bool PPCTargetMachine::addObjectWriter(FunctionPassManager &PM, bool Fast,
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std::ostream &Out) {
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// FIXME: support PPC ELF files at some point
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addPPCMachOObjectWriterPass(PM, Out, *this);
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return true;
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}
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bool PPCTargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
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MachineCodeEmitter &MCE) {
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// The JIT should use the static relocation model.
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// FIXME: This should be moved to TargetJITInfo!!
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setRelocationModel(Reloc::Static);
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCCodeEmitterPass(*this, MCE));
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return false;
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}
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