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https://github.com/c64scene-ar/llvm-6502.git
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6c7cb29038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22440 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
2.8 KiB
C++
Executable File
83 lines
2.8 KiB
C++
Executable File
//===-- X86IntelAsmPrinter.h - Convert X86 LLVM code to Intel assembly ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Intel assembly code printer class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INTELASMPRINTER_H
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#define X86INTELASMPRINTER_H
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#include "X86AsmPrinter.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MRegisterInfo.h"
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namespace llvm {
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namespace x86 {
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struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
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X86IntelAsmPrinter(std::ostream &O, TargetMachine &TM)
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: X86SharedAsmPrinter(O, TM) { }
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virtual const char *getPassName() const {
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return "X86 Intel-Style Assembly Printer";
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}
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description. This method returns true if the
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/// machine instruction was sufficiently described to print it, otherwise it
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/// returns false.
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bool printInstruction(const MachineInstr *MI);
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// This method is used by the tablegen'erated instruction printer.
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void printOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT){
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const MachineOperand &MO = MI->getOperand(OpNo);
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if (MO.getType() == MachineOperand::MO_MachineRegister) {
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assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << "%" << TM.getRegisterInfo()->get(MO.getReg()).Name;
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} else {
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printOp(MO);
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}
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}
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void printCallOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET".
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}
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void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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switch (VT) {
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default: assert(0 && "Unknown arg size!");
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case MVT::i8: O << "BYTE PTR "; break;
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case MVT::i16: O << "WORD PTR "; break;
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case MVT::i32:
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case MVT::f32: O << "DWORD PTR "; break;
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case MVT::i64:
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case MVT::f64: O << "QWORD PTR "; break;
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case MVT::f80: O << "XWORD PTR "; break;
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}
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printMemReference(MI, OpNo);
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}
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
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void printSSECC(const MachineInstr *MI, unsigned Op, MVT::ValueType VT);
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void printMemReference(const MachineInstr *MI, unsigned Op);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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};
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} // end namespace x86
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} // end namespace llvm
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#endif
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