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https://github.com/c64scene-ar/llvm-6502.git
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87773c318f
Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
2.6 KiB
ArmAsm
61 lines
2.6 KiB
ArmAsm
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
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// Check that the assembler can handle the documented syntax for AArch64
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//------------------------------------------------------------------------------
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// Vector And
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//------------------------------------------------------------------------------
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and v0.8b, v1.8b, v2.8b
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and v0.16b, v1.16b, v2.16b
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// CHECK: and v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x0e]
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// CHECK: and v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x4e]
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//------------------------------------------------------------------------------
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// Vector Orr
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//------------------------------------------------------------------------------
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orr v0.8b, v1.8b, v2.8b
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orr v0.16b, v1.16b, v2.16b
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// CHECK: orr v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x0e]
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// CHECK: orr v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x4e]
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//------------------------------------------------------------------------------
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// Vector Eor
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//------------------------------------------------------------------------------
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eor v0.8b, v1.8b, v2.8b
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eor v0.16b, v1.16b, v2.16b
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// CHECK: eor v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x2e]
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// CHECK: eor v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x6e]
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//----------------------------------------------------------------------
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// Vector Bitwise
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//----------------------------------------------------------------------
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bit v0.8b, v1.8b, v2.8b
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bit v0.16b, v1.16b, v2.16b
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bif v0.8b, v1.8b, v2.8b
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bif v0.16b, v1.16b, v2.16b
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bsl v0.8b, v1.8b, v2.8b
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bsl v0.16b, v1.16b, v2.16b
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orn v0.8b, v1.8b, v2.8b
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orn v0.16b, v1.16b, v2.16b
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bic v0.8b, v1.8b, v2.8b
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bic v0.16b, v1.16b, v2.16b
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// CHECK: bit v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x2e]
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// CHECK: bit v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x6e]
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// CHECK: bif v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x2e]
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// CHECK: bif v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x6e]
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// CHECK: bsl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x2e]
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// CHECK: bsl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x6e]
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// CHECK: orn v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x0e]
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// CHECK: orn v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x4e]
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// CHECK: bic v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x0e]
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// CHECK: bic v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x4e]
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