mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-31 12:30:06 +00:00
Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216982 91177308-0d34-0410-b5e6-96231b3b80d8
663 lines
21 KiB
C++
663 lines
21 KiB
C++
//===-- PPCCTRLoops.cpp - Identify and generate CTR loops -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass identifies loops where we can generate the PPC branch instructions
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// that decrement and test the count register (CTR) (bdnz and friends).
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//
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// The pattern that defines the induction variable can changed depending on
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// prior optimizations. For example, the IndVarSimplify phase run by 'opt'
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// normalizes induction variables, and the Loop Strength Reduction pass
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// run by 'llc' may also make changes to the induction variable.
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//
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// Criteria for CTR loops:
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// - Countable loops (w/ ind. var for a trip count)
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// - Try inner-most loops first
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// - No nested CTR loops.
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// - No function calls in loops.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Transforms/Scalar.h"
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#include "PPC.h"
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#include "PPCTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/ScalarEvolutionExpander.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/ValueHandle.h"
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#include "llvm/PassSupport.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLibraryInfo.h"
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#include "llvm/Transforms/Utils/BasicBlockUtils.h"
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#include "llvm/Transforms/Utils/Local.h"
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#include "llvm/Transforms/Utils/LoopUtils.h"
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#ifndef NDEBUG
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#endif
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#include <algorithm>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "ctrloops"
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#ifndef NDEBUG
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static cl::opt<int> CTRLoopLimit("ppc-max-ctrloop", cl::Hidden, cl::init(-1));
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#endif
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STATISTIC(NumCTRLoops, "Number of loops converted to CTR loops");
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namespace llvm {
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void initializePPCCTRLoopsPass(PassRegistry&);
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#ifndef NDEBUG
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void initializePPCCTRLoopsVerifyPass(PassRegistry&);
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#endif
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}
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namespace {
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struct PPCCTRLoops : public FunctionPass {
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#ifndef NDEBUG
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static int Counter;
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#endif
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public:
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static char ID;
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PPCCTRLoops() : FunctionPass(ID), TM(nullptr) {
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initializePPCCTRLoopsPass(*PassRegistry::getPassRegistry());
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}
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PPCCTRLoops(PPCTargetMachine &TM) : FunctionPass(ID), TM(&TM) {
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initializePPCCTRLoopsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnFunction(Function &F) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LoopInfo>();
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AU.addPreserved<LoopInfo>();
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AU.addRequired<DominatorTreeWrapperPass>();
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AU.addPreserved<DominatorTreeWrapperPass>();
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AU.addRequired<ScalarEvolution>();
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}
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private:
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bool mightUseCTR(const Triple &TT, BasicBlock *BB);
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bool convertToCTRLoop(Loop *L);
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private:
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PPCTargetMachine *TM;
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LoopInfo *LI;
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ScalarEvolution *SE;
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const DataLayout *DL;
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DominatorTree *DT;
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const TargetLibraryInfo *LibInfo;
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};
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char PPCCTRLoops::ID = 0;
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#ifndef NDEBUG
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int PPCCTRLoops::Counter = 0;
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#endif
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#ifndef NDEBUG
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struct PPCCTRLoopsVerify : public MachineFunctionPass {
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public:
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static char ID;
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PPCCTRLoopsVerify() : MachineFunctionPass(ID) {
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initializePPCCTRLoopsVerifyPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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MachineDominatorTree *MDT;
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};
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char PPCCTRLoopsVerify::ID = 0;
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#endif // NDEBUG
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(PPCCTRLoops, "ppc-ctr-loops", "PowerPC CTR Loops",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(LoopInfo)
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INITIALIZE_PASS_DEPENDENCY(ScalarEvolution)
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INITIALIZE_PASS_END(PPCCTRLoops, "ppc-ctr-loops", "PowerPC CTR Loops",
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false, false)
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FunctionPass *llvm::createPPCCTRLoops(PPCTargetMachine &TM) {
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return new PPCCTRLoops(TM);
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}
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#ifndef NDEBUG
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INITIALIZE_PASS_BEGIN(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
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"PowerPC CTR Loops Verify", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
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"PowerPC CTR Loops Verify", false, false)
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FunctionPass *llvm::createPPCCTRLoopsVerify() {
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return new PPCCTRLoopsVerify();
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}
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#endif // NDEBUG
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bool PPCCTRLoops::runOnFunction(Function &F) {
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LI = &getAnalysis<LoopInfo>();
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SE = &getAnalysis<ScalarEvolution>();
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DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
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DataLayoutPass *DLP = getAnalysisIfAvailable<DataLayoutPass>();
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DL = DLP ? &DLP->getDataLayout() : nullptr;
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LibInfo = getAnalysisIfAvailable<TargetLibraryInfo>();
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bool MadeChange = false;
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for (LoopInfo::iterator I = LI->begin(), E = LI->end();
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I != E; ++I) {
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Loop *L = *I;
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if (!L->getParentLoop())
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MadeChange |= convertToCTRLoop(L);
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}
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return MadeChange;
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}
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static bool isLargeIntegerTy(bool Is32Bit, Type *Ty) {
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if (IntegerType *ITy = dyn_cast<IntegerType>(Ty))
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return ITy->getBitWidth() > (Is32Bit ? 32U : 64U);
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return false;
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}
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bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicBlock *BB) {
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for (BasicBlock::iterator J = BB->begin(), JE = BB->end();
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J != JE; ++J) {
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if (CallInst *CI = dyn_cast<CallInst>(J)) {
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if (InlineAsm *IA = dyn_cast<InlineAsm>(CI->getCalledValue())) {
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// Inline ASM is okay, unless it clobbers the ctr register.
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InlineAsm::ConstraintInfoVector CIV = IA->ParseConstraints();
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for (unsigned i = 0, ie = CIV.size(); i < ie; ++i) {
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InlineAsm::ConstraintInfo &C = CIV[i];
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if (C.Type != InlineAsm::isInput)
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for (unsigned j = 0, je = C.Codes.size(); j < je; ++j)
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if (StringRef(C.Codes[j]).equals_lower("{ctr}"))
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return true;
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}
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continue;
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}
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if (!TM)
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return true;
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const TargetLowering *TLI = TM->getSubtargetImpl()->getTargetLowering();
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if (Function *F = CI->getCalledFunction()) {
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// Most intrinsics don't become function calls, but some might.
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// sin, cos, exp and log are always calls.
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unsigned Opcode;
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if (F->getIntrinsicID() != Intrinsic::not_intrinsic) {
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switch (F->getIntrinsicID()) {
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default: continue;
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// VisualStudio defines setjmp as _setjmp
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#if defined(_MSC_VER) && defined(setjmp) && \
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!defined(setjmp_undefined_for_msvc)
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# pragma push_macro("setjmp")
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# undef setjmp
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# define setjmp_undefined_for_msvc
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#endif
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case Intrinsic::setjmp:
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#if defined(_MSC_VER) && defined(setjmp_undefined_for_msvc)
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// let's return it to _setjmp state
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# pragma pop_macro("setjmp")
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# undef setjmp_undefined_for_msvc
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#endif
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case Intrinsic::longjmp:
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// Exclude eh_sjlj_setjmp; we don't need to exclude eh_sjlj_longjmp
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// because, although it does clobber the counter register, the
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// control can't then return to inside the loop unless there is also
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// an eh_sjlj_setjmp.
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case Intrinsic::eh_sjlj_setjmp:
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case Intrinsic::memcpy:
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case Intrinsic::memmove:
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case Intrinsic::memset:
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case Intrinsic::powi:
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case Intrinsic::log:
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case Intrinsic::log2:
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case Intrinsic::log10:
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case Intrinsic::exp:
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case Intrinsic::exp2:
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case Intrinsic::pow:
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case Intrinsic::sin:
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case Intrinsic::cos:
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return true;
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case Intrinsic::copysign:
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if (CI->getArgOperand(0)->getType()->getScalarType()->
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isPPC_FP128Ty())
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return true;
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else
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continue; // ISD::FCOPYSIGN is never a library call.
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case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
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case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
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case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
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case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
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case Intrinsic::rint: Opcode = ISD::FRINT; break;
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case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
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case Intrinsic::round: Opcode = ISD::FROUND; break;
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}
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}
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// PowerPC does not use [US]DIVREM or other library calls for
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// operations on regular types which are not otherwise library calls
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// (i.e. soft float or atomics). If adapting for targets that do,
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// additional care is required here.
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LibFunc::Func Func;
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if (!F->hasLocalLinkage() && F->hasName() && LibInfo &&
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LibInfo->getLibFunc(F->getName(), Func) &&
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LibInfo->hasOptimizedCodeGen(Func)) {
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// Non-read-only functions are never treated as intrinsics.
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if (!CI->onlyReadsMemory())
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return true;
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// Conversion happens only for FP calls.
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if (!CI->getArgOperand(0)->getType()->isFloatingPointTy())
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return true;
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switch (Func) {
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default: return true;
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case LibFunc::copysign:
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case LibFunc::copysignf:
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continue; // ISD::FCOPYSIGN is never a library call.
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case LibFunc::copysignl:
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return true;
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case LibFunc::fabs:
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case LibFunc::fabsf:
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case LibFunc::fabsl:
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continue; // ISD::FABS is never a library call.
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case LibFunc::sqrt:
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case LibFunc::sqrtf:
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case LibFunc::sqrtl:
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Opcode = ISD::FSQRT; break;
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case LibFunc::floor:
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case LibFunc::floorf:
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case LibFunc::floorl:
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Opcode = ISD::FFLOOR; break;
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case LibFunc::nearbyint:
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case LibFunc::nearbyintf:
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case LibFunc::nearbyintl:
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Opcode = ISD::FNEARBYINT; break;
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case LibFunc::ceil:
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case LibFunc::ceilf:
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case LibFunc::ceill:
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Opcode = ISD::FCEIL; break;
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case LibFunc::rint:
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case LibFunc::rintf:
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case LibFunc::rintl:
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Opcode = ISD::FRINT; break;
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case LibFunc::round:
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case LibFunc::roundf:
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case LibFunc::roundl:
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Opcode = ISD::FROUND; break;
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case LibFunc::trunc:
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case LibFunc::truncf:
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case LibFunc::truncl:
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Opcode = ISD::FTRUNC; break;
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}
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MVT VTy =
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TLI->getSimpleValueType(CI->getArgOperand(0)->getType(), true);
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if (VTy == MVT::Other)
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return true;
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if (TLI->isOperationLegalOrCustom(Opcode, VTy))
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continue;
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else if (VTy.isVector() &&
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TLI->isOperationLegalOrCustom(Opcode, VTy.getScalarType()))
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continue;
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return true;
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}
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}
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return true;
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} else if (isa<BinaryOperator>(J) &&
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J->getType()->getScalarType()->isPPC_FP128Ty()) {
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// Most operations on ppc_f128 values become calls.
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return true;
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} else if (isa<UIToFPInst>(J) || isa<SIToFPInst>(J) ||
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isa<FPToUIInst>(J) || isa<FPToSIInst>(J)) {
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CastInst *CI = cast<CastInst>(J);
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if (CI->getSrcTy()->getScalarType()->isPPC_FP128Ty() ||
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CI->getDestTy()->getScalarType()->isPPC_FP128Ty() ||
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isLargeIntegerTy(TT.isArch32Bit(), CI->getSrcTy()->getScalarType()) ||
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isLargeIntegerTy(TT.isArch32Bit(), CI->getDestTy()->getScalarType()))
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return true;
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} else if (isLargeIntegerTy(TT.isArch32Bit(),
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J->getType()->getScalarType()) &&
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(J->getOpcode() == Instruction::UDiv ||
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J->getOpcode() == Instruction::SDiv ||
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J->getOpcode() == Instruction::URem ||
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J->getOpcode() == Instruction::SRem)) {
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return true;
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} else if (TT.isArch32Bit() &&
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isLargeIntegerTy(false, J->getType()->getScalarType()) &&
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(J->getOpcode() == Instruction::Shl ||
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J->getOpcode() == Instruction::AShr ||
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J->getOpcode() == Instruction::LShr)) {
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// Only on PPC32, for 128-bit integers (specifically not 64-bit
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// integers), these might be runtime calls.
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return true;
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} else if (isa<IndirectBrInst>(J) || isa<InvokeInst>(J)) {
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// On PowerPC, indirect jumps use the counter register.
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return true;
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} else if (SwitchInst *SI = dyn_cast<SwitchInst>(J)) {
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if (!TM)
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return true;
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const TargetLowering *TLI = TM->getSubtargetImpl()->getTargetLowering();
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if (SI->getNumCases() + 1 >= (unsigned)TLI->getMinimumJumpTableEntries())
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return true;
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}
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}
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return false;
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}
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bool PPCCTRLoops::convertToCTRLoop(Loop *L) {
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bool MadeChange = false;
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Triple TT = Triple(L->getHeader()->getParent()->getParent()->
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getTargetTriple());
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if (!TT.isArch32Bit() && !TT.isArch64Bit())
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return MadeChange; // Unknown arch. type.
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// Process nested loops first.
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for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
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MadeChange |= convertToCTRLoop(*I);
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}
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// If a nested loop has been converted, then we can't convert this loop.
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if (MadeChange)
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return MadeChange;
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#ifndef NDEBUG
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// Stop trying after reaching the limit (if any).
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int Limit = CTRLoopLimit;
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if (Limit >= 0) {
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if (Counter >= CTRLoopLimit)
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return false;
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Counter++;
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}
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#endif
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// We don't want to spill/restore the counter register, and so we don't
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// want to use the counter register if the loop contains calls.
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for (Loop::block_iterator I = L->block_begin(), IE = L->block_end();
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I != IE; ++I)
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if (mightUseCTR(TT, *I))
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return MadeChange;
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SmallVector<BasicBlock*, 4> ExitingBlocks;
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L->getExitingBlocks(ExitingBlocks);
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BasicBlock *CountedExitBlock = nullptr;
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const SCEV *ExitCount = nullptr;
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BranchInst *CountedExitBranch = nullptr;
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for (SmallVectorImpl<BasicBlock *>::iterator I = ExitingBlocks.begin(),
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IE = ExitingBlocks.end(); I != IE; ++I) {
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const SCEV *EC = SE->getExitCount(L, *I);
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DEBUG(dbgs() << "Exit Count for " << *L << " from block " <<
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(*I)->getName() << ": " << *EC << "\n");
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if (isa<SCEVCouldNotCompute>(EC))
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continue;
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if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
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if (ConstEC->getValue()->isZero())
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continue;
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} else if (!SE->isLoopInvariant(EC, L))
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continue;
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if (SE->getTypeSizeInBits(EC->getType()) > (TT.isArch64Bit() ? 64 : 32))
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continue;
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// We now have a loop-invariant count of loop iterations (which is not the
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// constant zero) for which we know that this loop will not exit via this
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// exisiting block.
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// We need to make sure that this block will run on every loop iteration.
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// For this to be true, we must dominate all blocks with backedges. Such
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// blocks are in-loop predecessors to the header block.
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bool NotAlways = false;
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for (pred_iterator PI = pred_begin(L->getHeader()),
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PIE = pred_end(L->getHeader()); PI != PIE; ++PI) {
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if (!L->contains(*PI))
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continue;
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if (!DT->dominates(*I, *PI)) {
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NotAlways = true;
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break;
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}
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}
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if (NotAlways)
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continue;
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// Make sure this blocks ends with a conditional branch.
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Instruction *TI = (*I)->getTerminator();
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if (!TI)
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continue;
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if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
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if (!BI->isConditional())
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continue;
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CountedExitBranch = BI;
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} else
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continue;
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// Note that this block may not be the loop latch block, even if the loop
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// has a latch block.
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CountedExitBlock = *I;
|
|
ExitCount = EC;
|
|
break;
|
|
}
|
|
|
|
if (!CountedExitBlock)
|
|
return MadeChange;
|
|
|
|
BasicBlock *Preheader = L->getLoopPreheader();
|
|
|
|
// If we don't have a preheader, then insert one. If we already have a
|
|
// preheader, then we can use it (except if the preheader contains a use of
|
|
// the CTR register because some such uses might be reordered by the
|
|
// selection DAG after the mtctr instruction).
|
|
if (!Preheader || mightUseCTR(TT, Preheader))
|
|
Preheader = InsertPreheaderForLoop(L, this);
|
|
if (!Preheader)
|
|
return MadeChange;
|
|
|
|
DEBUG(dbgs() << "Preheader for exit count: " << Preheader->getName() << "\n");
|
|
|
|
// Insert the count into the preheader and replace the condition used by the
|
|
// selected branch.
|
|
MadeChange = true;
|
|
|
|
SCEVExpander SCEVE(*SE, "loopcnt");
|
|
LLVMContext &C = SE->getContext();
|
|
Type *CountType = TT.isArch64Bit() ? Type::getInt64Ty(C) :
|
|
Type::getInt32Ty(C);
|
|
if (!ExitCount->getType()->isPointerTy() &&
|
|
ExitCount->getType() != CountType)
|
|
ExitCount = SE->getZeroExtendExpr(ExitCount, CountType);
|
|
ExitCount = SE->getAddExpr(ExitCount,
|
|
SE->getConstant(CountType, 1));
|
|
Value *ECValue = SCEVE.expandCodeFor(ExitCount, CountType,
|
|
Preheader->getTerminator());
|
|
|
|
IRBuilder<> CountBuilder(Preheader->getTerminator());
|
|
Module *M = Preheader->getParent()->getParent();
|
|
Value *MTCTRFunc = Intrinsic::getDeclaration(M, Intrinsic::ppc_mtctr,
|
|
CountType);
|
|
CountBuilder.CreateCall(MTCTRFunc, ECValue);
|
|
|
|
IRBuilder<> CondBuilder(CountedExitBranch);
|
|
Value *DecFunc =
|
|
Intrinsic::getDeclaration(M, Intrinsic::ppc_is_decremented_ctr_nonzero);
|
|
Value *NewCond = CondBuilder.CreateCall(DecFunc);
|
|
Value *OldCond = CountedExitBranch->getCondition();
|
|
CountedExitBranch->setCondition(NewCond);
|
|
|
|
// The false branch must exit the loop.
|
|
if (!L->contains(CountedExitBranch->getSuccessor(0)))
|
|
CountedExitBranch->swapSuccessors();
|
|
|
|
// The old condition may be dead now, and may have even created a dead PHI
|
|
// (the original induction variable).
|
|
RecursivelyDeleteTriviallyDeadInstructions(OldCond);
|
|
DeleteDeadPHIs(CountedExitBlock);
|
|
|
|
++NumCTRLoops;
|
|
return MadeChange;
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
static bool clobbersCTR(const MachineInstr *MI) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isReg()) {
|
|
if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
|
|
return true;
|
|
} else if (MO.isRegMask()) {
|
|
if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8))
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool verifyCTRBranch(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator I) {
|
|
MachineBasicBlock::iterator BI = I;
|
|
SmallSet<MachineBasicBlock *, 16> Visited;
|
|
SmallVector<MachineBasicBlock *, 8> Preds;
|
|
bool CheckPreds;
|
|
|
|
if (I == MBB->begin()) {
|
|
Visited.insert(MBB);
|
|
goto queue_preds;
|
|
} else
|
|
--I;
|
|
|
|
check_block:
|
|
Visited.insert(MBB);
|
|
if (I == MBB->end())
|
|
goto queue_preds;
|
|
|
|
CheckPreds = true;
|
|
for (MachineBasicBlock::iterator IE = MBB->begin();; --I) {
|
|
unsigned Opc = I->getOpcode();
|
|
if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
|
|
CheckPreds = false;
|
|
break;
|
|
}
|
|
|
|
if (I != BI && clobbersCTR(I)) {
|
|
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " (" <<
|
|
MBB->getFullName() << ") instruction " << *I <<
|
|
" clobbers CTR, invalidating " << "BB#" <<
|
|
BI->getParent()->getNumber() << " (" <<
|
|
BI->getParent()->getFullName() << ") instruction " <<
|
|
*BI << "\n");
|
|
return false;
|
|
}
|
|
|
|
if (I == IE)
|
|
break;
|
|
}
|
|
|
|
if (!CheckPreds && Preds.empty())
|
|
return true;
|
|
|
|
if (CheckPreds) {
|
|
queue_preds:
|
|
if (MachineFunction::iterator(MBB) == MBB->getParent()->begin()) {
|
|
DEBUG(dbgs() << "Unable to find a MTCTR instruction for BB#" <<
|
|
BI->getParent()->getNumber() << " (" <<
|
|
BI->getParent()->getFullName() << ") instruction " <<
|
|
*BI << "\n");
|
|
return false;
|
|
}
|
|
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
PIE = MBB->pred_end(); PI != PIE; ++PI)
|
|
Preds.push_back(*PI);
|
|
}
|
|
|
|
do {
|
|
MBB = Preds.pop_back_val();
|
|
if (!Visited.count(MBB)) {
|
|
I = MBB->getLastNonDebugInstr();
|
|
goto check_block;
|
|
}
|
|
} while (!Preds.empty());
|
|
|
|
return true;
|
|
}
|
|
|
|
bool PPCCTRLoopsVerify::runOnMachineFunction(MachineFunction &MF) {
|
|
MDT = &getAnalysis<MachineDominatorTree>();
|
|
|
|
// Verify that all bdnz/bdz instructions are dominated by a loop mtctr before
|
|
// any other instructions that might clobber the ctr register.
|
|
for (MachineFunction::iterator I = MF.begin(), IE = MF.end();
|
|
I != IE; ++I) {
|
|
MachineBasicBlock *MBB = I;
|
|
if (!MDT->isReachableFromEntry(MBB))
|
|
continue;
|
|
|
|
for (MachineBasicBlock::iterator MII = MBB->getFirstTerminator(),
|
|
MIIE = MBB->end(); MII != MIIE; ++MII) {
|
|
unsigned Opc = MII->getOpcode();
|
|
if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
|
|
Opc == PPC::BDZ8 || Opc == PPC::BDZ)
|
|
if (!verifyCTRBranch(MBB, MII))
|
|
llvm_unreachable("Invalid PPC CTR loop!");
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
#endif // NDEBUG
|
|
|