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llvm-6502/test/CodeGen
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Matt Arsenault 1751616522 R600/SI: Allow f64 inline immediates in i64 operands 
This requires considering the size of the operand when
checking immediate legality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229135 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-13 19:05:03 +00:00
..
AArch64 [SimplifyCFG] Be more aggressive 2015-02-13 10:48:30 +00:00
ARM [SimplifyCFG] Swap to using TargetTransformInfo for cost 2015-02-11 12:15:41 +00:00
BPF
CPP
Generic
Hexagon [Hexagon] Factoring classes out of store patterns. 2015-02-09 20:33:46 +00:00
Inputs
Mips [mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC 2015-02-13 17:51:27 +00:00
MSP430
NVPTX
PowerPC [CodeGenPrepare] Removed duplicate logic. SimplifyCFG already knows how to speculate calls to cttz/ctlz. 2015-02-13 14:15:48 +00:00
R600 R600/SI: Allow f64 inline immediates in i64 operands 2015-02-13 19:05:03 +00:00
SPARC
SystemZ
Thumb
Thumb2 Make buildbots better. 2015-02-11 12:24:09 +00:00
X86 [CodeGenPrepare] Removed duplicate logic. SimplifyCFG already knows how to speculate calls to cttz/ctlz. 2015-02-13 14:15:48 +00:00
XCore