mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 06:29:45 +00:00
There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
3.2 KiB
C++
92 lines
3.2 KiB
C++
//===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the MSP430 implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_TARGET_MSP430INSTRINFO_H
|
|
#define LLVM_TARGET_MSP430INSTRINFO_H
|
|
|
|
#include "MSP430RegisterInfo.h"
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
|
|
#define GET_INSTRINFO_HEADER
|
|
#include "MSP430GenInstrInfo.inc"
|
|
|
|
namespace llvm {
|
|
|
|
class MSP430TargetMachine;
|
|
|
|
/// MSP430II - This namespace holds all of the target specific flags that
|
|
/// instruction info tracks.
|
|
///
|
|
namespace MSP430II {
|
|
enum {
|
|
SizeShift = 2,
|
|
SizeMask = 7 << SizeShift,
|
|
|
|
SizeUnknown = 0 << SizeShift,
|
|
SizeSpecial = 1 << SizeShift,
|
|
Size2Bytes = 2 << SizeShift,
|
|
Size4Bytes = 3 << SizeShift,
|
|
Size6Bytes = 4 << SizeShift
|
|
};
|
|
}
|
|
|
|
class MSP430InstrInfo : public MSP430GenInstrInfo {
|
|
const MSP430RegisterInfo RI;
|
|
public:
|
|
explicit MSP430InstrInfo(MSP430TargetMachine &TM);
|
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
/// always be able to get register info as well (through this method).
|
|
///
|
|
virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
|
|
|
|
void copyPhysReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I, DebugLoc DL,
|
|
unsigned DestReg, unsigned SrcReg,
|
|
bool KillSrc) const;
|
|
|
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned SrcReg, bool isKill,
|
|
int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const;
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, int FrameIdx,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const;
|
|
|
|
unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
|
|
|
|
// Branch folding goodness
|
|
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
|
bool isUnpredicatedTerminator(const MachineInstr *MI) const;
|
|
bool AnalyzeBranch(MachineBasicBlock &MBB,
|
|
MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
bool AllowModify) const;
|
|
|
|
unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
|
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
const SmallVectorImpl<MachineOperand> &Cond,
|
|
DebugLoc DL) const;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|